Charge-recycling bus (CRB) achieves quadratic energy savings by stacking two data channels between VDD and VSS. However, it suffers from middle voltage (VMID) drift due to unbalanced data activities of the two channels, which increases signal propagation delay and causes timing violations. In this paper, we present ASF-CRB, a CRB architecture that addresses the VMID drift problem at minimum energy costs based on a novel data transmission scheme named Alternate Signal Flipping (ASF). By reconfiguring the signal transmission path every cycle through a multiplexer at each pipeline stage, ASF ensures all bits flip once in every two pipeline stages. This averages each channel's high and low activities to 50% and thus contributes to balanced data activities between stacked channels. Lightweight latch structures tailored to CRBs are presented to minimize the delay and energy overheads, and a complete ASF-CRB architecture is developed for applicability in VLSI systems. The proposed ASF-CRB is implemented at a 28nm CMOS process. Post-layout simulations show that ASF-CRB achieves up to 41.0% energy saving at similar VMID stability and ∼2.7× smaller VMID drifts at similar energy consumption compared with the state-of-the-art CRB structure.

By stacking two data channels between VDD and VSS, Charge Recycling Buses (CRBs) halve the voltage swing on interconnects, achieving significant power savings for energy-efficient on-chip data transmission. However, the middle voltage (VMID) between the two channels may fluctuate dynamically due to the diversity of input data, which significantly impacts data propagation delay and reliability. Unfortunately, existing SPICE-based simulators do not run fast enough to identify the worst-case VMID fluctuation and propagation delay, posing great challenges in CRB design. In this paper, we present a dedicated CRB Simulator for fast and accurate VMID and timing analysis. A highly condensed VMID fluctuation model, which integrates each cycles VMID changes into a single closed-form formula, is embedded in the simulator to predict VMID values at clock edges. In addition, a speed-monitoring algorithm is developed to track the continuously changing signal propagation speed under intra-cycle VMID fluctuations for accurate delay estimation. Both the VMID fluctuation model and the delay estimation algorithm involve only a small number of arithmetic operations, thus featuring remarkably low computational complexity. Compared with HSPICE, our CRB Simulator runs > 1.0×105 times faster on average across various CRB circuits, with a VMID prediction error of only 1.3mV and a delay estimation error as low as 0.6%. The significant speed improvement combined with high accuracy makes our CRB Simulator an efficient and reliable solution for VMID and timing analysis in CRB circuit design.