The chiplet based integrated system contains lots of inter-die interconnections. The through silicon vias (TSVs) and micro bumps are the common components of the vertical electrical interconnections in the $2.5 \mathrm{D} / 3 \mathrm{D}$ multi-die integration circuits. They are usually laid out as arrays to regulate the routing rules. Faults may occur in the TSVs, and the redundant resources based self-repair mechanisms are introduced to improve the yield of the entire integrated chip. In the Universal Chiplet Interconnect Express (UCIe) standard, each advanced package module contains 32 data lanes and 2 redundant lanes, and the shift chain based intra-module self-repair mechanism is defined. However, the faults are usually clustered in certain region of the TSV array. The intra-module self-repair mechanism of UCIe standard is not able to cope with the cases that more than 2 clustered faults occur simultaneously in one module. An effective idea to improve the repair rate is to distribute the faults into different modules by regrouping the layout of TSV array. This work reports some new spiral layouts of rectangular and hexagonal TSV arrays. The self-repair schemes based on the proposed layouts are UCIe-compliant. Simulation results present that the proposed self-repair schemes are able to repair the clustered faults in TSV array with the low repair latencies.

The chiplet-based 2.5D/3D multi-die integrated chips have numerous inter-die interconnect lanes, which may suffer from the faults in Through Silicon Vias (TSVs) or micro bumps. The faults are usually clustered in some regions. The redundant lanes are introduced for repairing, to maintain the product yield. The hexagonal array of lanes offers higher interconnect density than the rectangular array, but it requires more redundant lanes if faults are located within the same module. In the Universal Chiplet Interconnect Express (UCIe) standard, each Advanced Package module contains 32 data lanes and 2 redundant lanes, which limit the repair rate for the clustered faults. This work proposes a UCIe-compatible repair scheme which increases the probability of distributing faulty lanes in different modules. It achieves a higher repair rate for the clustered faults with a low proportion of redundant lanes. Simulation results show that for 8 faults in various cluster windows, the proposed scheme achieves a repair rate above 98% while consuming less area than previous approaches.