FinFET, now firmly established in leading VLSI industries for their superior performance, exhibit heightened aging susceptibility that poses significant reliability challenges. The aggressive scaling of technology nodes has further compromised circuit reliability in recent years, highlighting the need for effective aging mitigation techniques. Recent advancements in the miniaturization of nanoscale technology have demonstrated the potential of optimizing performance parameters in standard cells using machine learning models and optimization algorithms through device sizing modifications. Building on this progress, we propose a methodology for optimizing performance parameters in 16nm high-performance (HP) FinFET for the first time. The approach leverages a multi-objective optimization algorithm framework to mitigate aging impacts across PVT variations while addressing NBTI and HCI effects by optimally adjusting FinFET design parameters, including channel length (lg), width (tfin), and height (hfin). With SPICE simulations, time-series datasets were generated to train machine learning models that achieved an R2 score exceeding 0.99 and a mean absolute percentage error below 1% across standard cells. Our approach yields a significant simulation speedup and a reduction in simulation workload compared to traditional SPICE simulations. Using the proposed optimization algorithm framework, we improved the power-delay product (PDP) by up to 36.97% under non-aging conditions and 34.94% with aging considered with respect to the nominal dimension at the fresh year, demonstrating significant performance gains for FinFET-based standard cells. The experimental results on 12 distinct complex cells validate the aging mitigation across years.

Modeling process, operating condition, reliability, and technological variation in transistor level design introduce significant variance in device and performance parameters. This paper presents a machine-learning-based architectural approach that enhances model performance, as a step towards developing Foundation Models tailored for circuit data, accurately capturing technology and process-induced variations in leakage power, voltage, and current. The architecture incorporates the impact of varying operating conditions, including temperatures from -55°C to 125°C and supply voltage fluctuations of ±10% on 16nm HP FinFET, and 16nm, 22nm, 32nm, and 45nm HP-MGK CMOS technology nodes. By enhancing the performance of baseline machine-learning models using a chained architecture to cater to the high variance in target, our C-Arch serves as a versatile framework for circuit modeling when the data spread is high. Experimental results on current, voltage, and leakage power estimation, demonstrate average improvements of up to 93.76%, 96.17%, and 88.82% in Mean Absolute Percentage Error compared to baseline models, underscoring the computational savings and viability of Foundation Models in circuit design.