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R. David

dblp:41/1806 · DBLP profile ↗
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5ranked-venue papers
3as first author
0since 2021 · last 1997
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-authorTheory of computation · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 50% Hardware reliability and fault tolerance · 50%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware reliability and fault tolerance
error latency
0.011979
Comments on "The Error Latency of a Fault in a Sequential Digital Circuit" · IEEE Trans. Computers 1979
Electronic design automation
hardware verification and test
0.011979
Comments on "The Error Latency of a Fault in a Sequential Digital Circuit" · IEEE Trans. Computers 1979

Methods — techniques the papers use, named apart from their topics

approximation method · 0.0
YearPublicationVenuePosition
1997 Fault coverage of a long random test sequence estimated from a short simulation
abstract
Forecasting the fault coverage of a long random test sequence from the results obtained from the simulation of a short test sequence looks like an inaccessible dream. As a matter of fact, a short test sequence detects mainly easy to detect faults, while the test length required for a fault coverage close to 1 depends mainly (almost only) on the most difficult faults. A new 2-parameter model, linking the fault coverage to the test length, was proposed recently. Although these parameters are very difficult to obtain, they can be roughly estimated from a relatively short simulation. According to a previous comment, the results can not be accurate. However, they are more accurate that ones obtained from other models proposed in the literature.
V. Prepin, R. David
VTS2
1990 Some Results on Higher Suslin Trees
abstract
Higher Suslin trees have become a tool in some forcing constructions in set theory (see, for example, [D1] and [D2]). Most of the constructions using ω1 Suslin trees can be extended to κ+ Suslin trees for any regular cardinal κ. Some of these are given in §1. In many such constructions, sequences of Suslin trees are used. In §II we show, in various ways, that the generalization to sequences, even ω-sequences, of κ+ Suslin trees cannot be done. In these constructions the Suslin trees are used as forcing poset (the forcing adds a branch in the tree). There is another way to kill a Suslin tree, namely by adding a big antichain. Some results on this forcing are given in §III. Our notation is standard. If T is a tree and x ∈ T, then ∣x∣ is the height of x in T. We define Tα (or T(α)) = {x ∈ T: ∣x∣ = α} and T∣α = {x ∈ T: ∣x∣ < α}. If p and q are forcing conditions, p ≤ q means that p has more information than q. If (Tα: α ∈ I) is a sequence of trees, Π Tα will always mean the set of (xα: α ∈ I) such that xα ∈ Tα and ∣xα∣ = ∣xβ∣ for α, β ∈ I. For functions b, T,… we denote by b ∣α, T∣ α,… their restriction to α. If x is a sequence of ordinals and α is an ordinal, x∧α is the sequence obtained by concatenating α at the end of x.
R. David
J. Symb. Log.1
1984 Some New Results on Operational Analysis
Yves Dallery, R. David
Performance2
1982 Some applications of Jensen's coding theorem
R. David
Ann. Math. Log.1
1979 Comments on "The Error Latency of a Fault in a Sequential Digital Circuit"
abstract
In the paper "The Error Latency of a Fault in a Sequential Digital Circuit," the method presented in [1] to evaluate the random test length to be applied to a sequential circuit, is called the "approximation method." We agree with this name, but wish to offer the following interpretations and clarifications (using the notations of Shedletsky and McCluskey1).
R. David, R. Téllez-Girón
IEEE Trans. Computers1