Jock A. Rader

dblp:41/1821 · DBLP profile ↗
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3ranked-venue papers
3as first author
0since 2021 · last 1995
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 2 · 2 first-authorSystems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
design validation
0.011969
Aw expanded logic equation list for checkout · DAC 1969
Electronic design automation
hardware verification and test
0.011969
Aw expanded logic equation list for checkout · DAC 1969
Electronic design automation
physical design
0.011969
Aw expanded logic equation list for checkout · DAC 1969
Electronic design automation › physical design
wiring and routing
0.011969
Aw expanded logic equation list for checkout · DAC 1969

Methods — techniques the papers use, named apart from their topics

equation connector program · 0.0
YearPublicationVenuePosition
1995 Operational use of CASE integration: An investigation of the state of the practice
Jock A. Rader, Alan W. Brown, Edwin J. Morris
J. Syst. Softw.1
1984 VLSI and software engineering: Guest editor's introduction
Jock A. Rader
J. Syst. Softw.1
1969 Aw expanded logic equation list for checkout
abstract
In the computer-aided design of digital equipment, by the time a wire unit is in the check-out lab, a large amount of information concerning this unit exists in the form of tape files. Since our D.A. System is entered via logic equations, we have a file containing this information, plus files indicating the partitioning of the equations, the placement of smaller building blocks within larger building blocks, and the assignment of signals to pins for routing or wiring. Also, there will be a wire list file (or a router output file) plus a punch card deck when a wiring machine is to be used. In addition a large pile of computer output reports will exist communicating this information to the literate world. About two years ago we learned that in some of the checkout labs engineers were devoting large amounts of time pouring through the reports we generate in order to correlate signals appearing in logic equations with connector pins. In order to remove this burden from these engineers, a program known as the Equation Connector Program (EQNCON) was written. This program exhibits the correlation of logic signals and connector pins in a printed report which is then heavily used during checkout.
Jock A. Rader, D. A. Isaak
DAC1