Designing of arbiters has become increasingly important due to their wide use in the areas such as multi-processor systems-on-a-chip and on-chip or off-chip high-speed cross-bar switches and networks. In this paper, we proposed a new systematic model-driven flow for designing the new scalable multi-facet arbiters through a 3-phase process combined with the template-based modular design approach that includes the design model derivation phase, the architecture model (or template) design phase as well as the arbiter hardware implementation and generation phase. First, we described the phase 1 of the design flow of how to induce an arbiter design model in detail by careful analysis of arbiter design issues and systematic design space exploring the construction of the model. Then, we continue to discuss the phase 2 of how to derive an architecture model or template using the reusability, modularity and expansibility techniques. With both the design and the architecture models, designers can easily design or at least understand and thus choose many kinds of different but better arbiters efficiently. Finally, we have developed a scalable decentralized parallel tree structure and corresponding modular algorithms for efficient arbiter hardware implementation, which also is the final phase of our proposed 3-phase model-driven design flow. Moreover, based on this modular and reusable hardware implementation structure as well as the algorithms, we have designed a parametric arbiter generator that automatically generates various multi-facet arbiters. Using this hardware implementation design and the generator, not only a fast and small round-robin arbiter but also other type arbiters were designed and generated on the fly. The hardware implementation algorithms, the generator, and the experiment results all were given to verify their performances. To our knowledge, this is the first time that such a systematic model-driven design approach is proposed in the practical hardware design and such a multi-facet arbiter is designed.

Designing of arbiters has become increasingly important because of their wide use in such as multi-processor system-on-a-chips (MPSoCs) and on- or off- chip high-speed cross-bar switches and networks. In this and an accompanying paper [6], we proposed a new systematic model-driven flow for design of the proposed new scalable multi-facet arbiters through a 3-phase process combined with the template-based modular design approach: the design model derivation phase, the architecture model (or template) design phase as well as arbiter hardware implementation and generation phase. Here, we described the phase 1 of the design flow of how to induce an arbiter design model in detail by careful analysis of arbiter design issues and systematic design space exploring the construction of the model. Then, we continue to discuss the phase 2 of how to derive an architecture model or template using the reusability, modularity and expansibility techniques. With both the design and architecture models, designers can easily design or at least understand and thus choose many kinds of different but better arbiters efficiently. The phase 3 is described in the accompanying paper [6]. To our knowledge, this is the first time that such a systematic model-driven design approach is proposed for the practical hardware design.

As a basic block of a multi-switching-and-processing system, fast and fair arbiters are critical to the efficiency of multi-core computing units, high-speed crossbar switches and routers, which are the key to the performance of on-chip networking/computing in a SoC and NoC. In this paper, a High-Speed and decentralized round-robin arbiter (HDRA) is presented. Unlike the conventional round-robin arbiters, the HDRA design, based on a de-centralized structure, is fast with only O(log4N) in critical path delay, area-efficient, and fair. The design results of it show that the arbitration performance of the HDRA is best compared with all existing arbiters, and still has smaller area cost. This new arbiter is being applied for a patent of the ROC (application No.: 0971xxxxx).

Color correction, which nonlinearly converts the color coordinates of an input device such as the scanner and digital camera into that of an output device such as the color laser printer, is important for multimedia applications. In this work, we present a novel dynamic pipelined VLSI architecture for the fuzzy color correction algorithm (FCC) proposed by Jou et al. (see IEEE Trans. Circuits Syst. I, vol.46, p.773-775, June 1998) to meet the speed requirement of time-critical applications. To promote the performance, the presented architecture is dynamically pipelined with unfixed or run-time determined latencies (or data initiation intervals) and the speculation technique is also applied, then the problems of arduous pipelining, due to the variant execution time of each iteration and slower executing of FCC are solved efficiently. As for data path design, a systematic design methodology of high-level synthesis is used. As a result, a significant (about 2 times) speedup of the dynamic pipelined architecture with a slight hardware overhead relative to the sequential one has been achieved.

Due to the temporal and spatial correlation of image sequence, the motion vector of a reference block is highly related to the motion vectors of its adjacent blocks in the same image frame. By using that idea, we propose a novel efficient fuzzy search (EFS) algorithm for block motion estimation. The experimental results show that the EFS performs better than other fast search algorithms, such as TSS, CS, NTSS, FSS, BBGDS, SES, and PSA in terms of picture quality, accuracy, computational complexity, and coding efficiency.

Most previous work about the hardware design of a fuzzy logic controller (FLC) intended to either improve its inference performance for real-time applications or to reduce its hardware cost. To our knowledge, there has been no attempt to design a hardware FLC that can perform an adaptive fuzzy inference for the applications of on-line adaptation. The purpose of this paper is to present such an adaptive memory-efficient FLC and its applications. Taking advantage of the adaptability provided by a symbolic fuzzy rule format and the dynamic membership function generator, as well as the high-speed integration capability afforded by VLSI, the proposed adaptive fuzzy logic controller (AFLC) can perform an adaptive fuzzy inference process using various inference parameters, such as the shape and location of a membership function, dynamically and quickly. Three examples are used to illustrate its applications, and the experimental results show the excellent adaptability provided by AFLC.

In this paper, we solve the problems of hazard-free synthesis and decomposition of asynchronous speed-independent circuits for technology mapping. All high fanin gates are decomposed into gates that can be implemented by the gate library. We first analyze the conditions where hazards may occur during decomposition and then give corresponding strategies to solve them. All the proposed algorithms have been implemented and applied to the asynchronous benchmarks to verify their correctness. Experimental results show that less area is required in our final implementations.

This paper presents a highly scalable efficient architecture for separable 2-D Discrete Wavelet Transform (DWT) which is simple, regular, modular and pipelined for the computation of 2-D DWT. With these properties, it is easily scalable for different filter lengths and different octave levels. In addition, the architecture has the characteristics of lower hardware cost, shorter latency, and higher throughput rate.

Color correction, which nonlinearly converts the color coordinates of an input device such as the scanner into that of an output device such as the printer, is important for multimedia applications. In this paper, we present a novel dynamic pipelined VLSI architecture for the fuzzy color correction algorithm proposed by Jer-Min Jou et al. (1998) to meet the speed requirement of time-critical applications. To prompt the performance, the presented architecture is dynamically pipelined with unfixed latencies (or data initiation intervals), then the problem of impossible pipelining (and then slow executing) the fuzzy color correction algorithm due to the variable execution length of each iteration in it is solved completely. As a result, a significant (about 2 times) speed-up of the dynamic pipeline architecture with a slight hardware overhead relative to the sequential architecture has been achieved.

This paper describes an online lossless data-compression method using adaptive arithmetic coding. To achieve good compression efficiency, we employ an adaptive fuzzy-tuning modeler that applies fuzzy inference to deal efficiently with the problem of conditional probability estimation. In comparison with other lossless coding schemes, the compression results of the proposed method are good and satisfactory for various types of source data, Since we adopt the table-lookup approach for the fuzzy-tuning modeler, the design is simple, fast, and suitable for VLSI implementation.

Due to the temporal and spatial correlation of the image sequence, the motion vector of a block is highly related to the motion vectors of its adjacent blocks in the same image frame. If we can obtain useful and enough information from the adjacent motion vectors, the total number of search points used to find the motion vector of the block may be reduced significantly. Using that idea, an efficient gray prediction search (GPS) algorithm for block motion estimation is proposed in this paper. Based on the gray system theory, the GPS can determine the motion vectors of image blocks quickly and correctly. The experimental results show that the proposed algorithm performs better than other search algorithms, such as 3SS, CS, PHODS, 4SS, BBGDS, SES and PSA, in terms of six different measures: (1) average mean square error per pixel; (2) average peak signal-to-noise ratio; (3) average prediction errors per pixel; (4) average entropy of prediction errors; (5) average percentage of unpredictable pels per frame; and (6) average search points per block.

In this paper, a time and memory-efficient diagnostic fault simulator for sequential circuits is first presented. A distributed diagnostic fault simulator is then presented based on the sequential algorithm to improve the speed of the diagnostic process. In the sequential diagnostic fault simulator, the number of fault-pair output response comparisons has been minimized by using an indistinguishability fault list that stores the faults that are indistinguishable from each fault. Due to the symmetrical relationship of the fault-pair distinguishability, fault list sizes are reduced. Therefore, the different diagnostic measures of a given test set can be generated very quickly using a small amount of memory. To further speed up the process of finding the indistinguishable fault list for each fault, a distributed approach is proposed and developed. The major idea for this approach is that each processor constructs the indistinguishable fault lists for a certain percentage of faults only. Experimental results show that the sequential diagnostic fault simulator runs faster and uses less memory than a previously developed one and that the distributed algorithm even achieves superlinear speedup for a very large sequential benchmark circuit, s35932. To the authors' knowledge, no distributed diagnostic fault simulation system for sequential circuits has been proposed before.

In this paper, a distributed diagnostic fault simulation for sequential circuits by dynamic fault partitioning is proposed, in which the indistinguishable faults for all the detectable faults are obtained from different machines. Several ISCAS89 benchmark circuits have been experimented on. For a circuit s35932, less than one hour of CPU time is spent by using 4 SUN SPARC stations II.

In this paper, we present an efficient diagnostic simulation method for combinational circuits. Two concepts are incorporated in this method. We adopt the critical line concept so that only stems, instead of all the faults, need to record the primary output responses and introduce the parallel simulation concept to propagate the effects of all the stems simultaneously. With these two approaches, our diagnostic simulator is efficient in speed and memory usage compared to an existed one.>

A method based on the 0-1 integer linear programming (ILP) model aiming primarily at minimizing the cost of interconnections is proposed for solving the data path allocation problem using multiport memories. The interconnection elements are generally composed of buses, multiplexers, and tri-state buffers. After solving the operation binding problem, we first find the number of buses required. Then we deal with the multiport memory allocation problem simultaneously minimizing the cost of multiplexers and tri-state buffers. From the solution quality and execution time of the experimental results, we see that our method is suitable for solving data path allocation problem using multiport memories when the cost of interconnections is first considered.>

A new algorithm for the integrated data path synthesis of high-performance DSP systems has been proposed. The integrated synthesis problem, that is the combined problem of module selection, scheduling, and allocation, is systematically formulated as a clique-partition problem of mixed-vertex compatibility graph on a module library and is solved simultaneously. We introduce a global cost function based on clique partition heuristic to evaluate each decision along the synthesis process. Salient features, such as library-adaptive and integrated processing (i.e., make all resources, including operators and interconnects, tradeoffs), are processed in the algorithm and experimental results are quite encouraged.>