This study proposes a versatile framework for real-time Internet of Things (IoT) network intrusion detection using Artificial Neural Network (ANN) on heterogeneous hardware. With the increase in the volume of exchanged data, IoT networks’ security has become a crucial issue. Anomaly-based intrusion detection systems (IDS) using machine learning have recently gained increased popularity due to their generation ability to detect new attacks. However, the deployment of anomaly-based AI-assisted IDS for IoT devices is computationally expensive. In this paper, a hierarchical decision-making approach for IDS is proposed and evaluated on the new IoT-23 dataset, with improved accuracy over the software-based methods. The inference engine is implemented on the Xilinx FPGA System on a Chip (SoC) hardware platform for high performance, high accuracy attack detection (more than 99.43%). For the resulting implemented design, the processing time of the ANN model on FPGA with an xc7z020clg400 device is 6.6 times and 40.5 times faster than GPU Quadro M2000 and CPU E5-2640 2.60GHz, respectively.

Despite Wireless Sensor Networks (WSNs) significantly developing over the past decade, these networks, like most wireless networks, remain susceptible to malicious interference and spectrum coexistence. Other vulnerabilities arise as WSN applications adopt open standards and typically resource and energy-constrained commercial-off-the-shelf equipment. Deployments include safety-critical applications such as the internet of things , medical, aerospace and space and deep-sea exploration. To manage safety and privacy requirements across such a diverse wireless landscape, security on wireless edge devices needs improvement while maintaining low complexity. This paper improves wireless edge device security by developing a novel intelligent interference diagnostic framework. Received in-phase (I) and quadrature-phase (Q) samples are exclusively utilized to detect modern, subtle and traditional crude jamming attacks. This I/Q sample utilization inherently enables decentralized decision-making, where the low-order features were extracted in a previous study focused on classifying typical 2.4–2.5 GHz wireless signals. The associated optimal intelligent models are leveraged as the foundation for this paper’s work. Initially, Matlab Monte Carlo simulations investigate the ideal case, which incorporates no hardware limitations, identifies the required data type of signal interactions and motivates a hardware investigation. Software-defined radios (SDRs) collect the required live over-the-air I/Q data and transmit matched signal (ZigBee) and continuous-wave interference in developed ZigBee wireless testbeds . Low complexity supervised machine learning models are developed based exclusively on the low-order features and achieve an average accuracy among the developed models above 98%. The designed methodology involves examining ZigBee over-the-air data for artificial jamming and SDR jamming of ZigBee signals transmitted from SDR and commercial (XBee) sources. This approach expands to a legitimate node classification technique and an overall algorithm for wireless edge device interference diagnostic tools. The investigation includes developing Support Vector Machine , XGBoost and Deep Neural Network (DNN) models, where XGBoost is optimal. Adapting the optimized models to global positioning system signals establishes the transferability of the designed methodology. Implementing the designed approaches on a Raspberry Pi embedded device examines a relatively resource-constrained deployment. The primary contribution is the real experimentally validated interference diagnostic framework that enables independent device operation, as no channel assumptions, network-level information or spectral images are required. Developed models exclusively use I/Q data low-order features and achieve high accuracy and generalization to unseen data.

We develop a method for calculating the probability of symbol error, via a multivariate Gram-Charlier series, for arbitrary coherent modulation schemes with statistically independent source symbols and subject to intersymbol interference (ISI) and additive white Gaussian noise (AWGN). The resulting error probability approximations have closed-form solutions and yield very accurate results with very little computational expense.

Acquisition of code division multiple access (CDMA) signals can be carried out using fixed or variable dwell times. The choice of acquisition strategy is a trade-off between performance and computational complexity, and a number of variable parameters (number of dwells, dwell lengths and thresholds) must be carefully designed. In this work, the performance of a variable dwell time coincidence detector is analysed in terms of its mean time to verify the acquisition of Global Positioning System (GPS) L1 C/A signals. A new expression for the variance of the coincidence detector dwell time is derived. A general framework for the optimisation of dwell parameters for the coincidence detector is outlined. Both immediate- and non-immediate reject cases are analysed and compared to the fixed dwell time single dwell strategy, which is, itself, a special case of the coincidence detector. Case-specific numerical optimisation results are illustrated across a range of signal-to-noise ratios and general rules-of-thumb for the best choice of parameters are highlighted.

Acquisition of signals in noise, in particular CDMA signals like the Global Positioning System (GPS) L1 C/A signal, can be carried out using fixed or variable dwell times. In this work, a sequential multiple dwell procedure for verifying acquisition is examined and compared to a fixed time single dwell strategy. The procedure under analysis is the sequential probability ratio test (SPRT) which has not been widely used for GPS applications, possibly due to its sensitivity to attenuation of the received signal relative to the design point. In this paper, it is shown that for the received signal to noise ratios (SNR) typically encountered in GPS, the SPRT can outperform the single dwell detector strategy in terms of mean acquisition time. In addition, it is shown that the single dwell (SD) detector's fixed dwell time approaches the worst case dwell time for the SPRT, as design point carrier to noise ratio decreases. Thus, for very weak signals, the SPRT can be a better choice of verification algorithm than the SD strategy, under certain constraints.

We present a simplified expression for the probability of error, Pe, for binary multichannel communications. The original expression was derived by Proakis in 1968. More recently, Simon and Alouini presented an expression involving the generalised Marcum Q-function. In this letter we present a simplified form of Simon and Alouini's expression. The application of this result to the calculation of performance metrics for communications over fading channels is also discussed.

Security protocols are frequently accelerated by implementing the underlying cryptographic functions in reconfigurable hardware. However, unprotected hardware implementations are susceptible to side-channel attacks, and Differential Power Analysis (DPA) has been shown to be especially powerful. In this work, we evaluate and compare the effectiveness of common hiding countermeasures against DPA in FPGA-based designs, using the Whirlpool hash function as a case study. In particular, we develop a new design flow called Isolated WDDL (IWDDL). In contrast with previous works, IWDDL isolates the direct and complementary circuit paths, and also provides DPA resistance in the Hamming distance power model. The analysis is supported using actual implementation results.

This paper presents a dedicated hardware implementation of the cryptographic Tate pairing on an elliptic curve of characteristic 2 using theetaTmethod. Efficient techniques for pairing computation are discussed and optimised hardware architectures are presented. A hardware pipelining scheme is described, which provides a dramatic reduction in pairing computation time. A cryptographic processor for computation of the bilinear pairing is presented and implemented on an FPGA. It is demonstrated that an FPGA forms an ideal basis for pairing processor implementation due to ease of reconfigurability and the opportunity for rapid prototyping. Implementation results are provided for pairing calculation on an FPGA over the base field

The authors present a fault tolerant algorithm for the solution of linear systems of equations using matrix triangularization procedures suitable for implementation on array architectures. Gaussian elimination with partial or pairwise pivoting and QR decomposition are made fault tolerant against two transient errors occurring during the triangularization procedure. The extended Euclidean algorithm is implemented to solve for the locations and values of the errors defined appropriately using the theory of error correcting codes. The Sherman-Morrison Woodbury formula is then used to obtain the correct solution vector to the linear system of equations without requiring a valid decomposition.>