Summary form only given. Memories are the highest volume ICs. With production of 30K wafers/month, i.e., production of NAND flash memories with 800 chips/wafer, a single fab today produces more than 250M chips per year. In such a high volume manufacturing (HVM) environment, identification of recurring faults, determination and elimination of the root cause in real-time is paramount to un-interrupted operation. In this presentation, a methodology was presented that creates a close-loop environment from ATE to EDA. Porting and analyzing tester data into EDA design environment drastically reduces fault identification time and the time to determine the cause of fault. Because diagnosis is performed within the EDA environment, diagnostic results become available at every level of the design hierarchy; thus, engineers can modify the design to eliminate the root cause

The open architecture test system provides a method and framework under which software and instruments of different vendors can be developed and integrated into an ATE. In This work, we describe the overall architecture and design of the system. First we describe the architecture and the control mechanism for the overall system and for individual test-sites. Data and command communication mechanism among these control elements is explained. After this general structure, we describe how this architecture allows deployment of third party instruments and modules, what are the interfaces, how system is configured and how correct operation of the system is ensured after plugging-in a third party module.

For first silicon, detection of systematic defects, timing failure and other errors is an extremely time-pressured task because detection and debugging of such failures determines how fast a product can go into mass production. In this paper we describe a new method for this purpose using an event tester. This method allows testing in the same environment as used for the original simulation in which the chip was designed. The method uses original design simulation data directly from the Verilog/VHDL simulation in the VCD format and thus, eliminates test program generation and test vector translation processes into WGL/STIL or ATE formats. It essentially extends the EDA design environment to the physical testing of an IC.

Summary form only given. A tester as well as an IC is a system at different abstraction levels. The testing of each of these systems should contain individual component testing as well as a full system level functional test to ensure its functional correctness. A full functional test of IC should be done regardless of the fault coverage of individual blocks and test methodology including DFT, structural test, Iddq etc. The interfaces and synergy in the operation of blocks can only be determined by functional test.

Embedded DRAM offers major advantages in terms of system integration on-chip. However, the fabrication process requires special attention for profitable manufacturing, particularly in the area of test and repair. We present the benefits which embedded DRAM offers, and then move to test issues. We provide an analysis of the technical and financial impact of different test approaches, and discuss which considerations are important in choosing a test strategy.

In this paper we describe the architecture and implementation of a true simulation-direct-to-test event based tester. This tester uses event based design simulation data in the VCD form. This data is used as-is without requiring tester cyclization. It is a true per pin tester that can significantly shorten test complexity and time-to-market.

It is little more than 15-years since the idea of Iddq testing was first proposed. Many semiconductor companies now consider Iddq testing as an integral part of the overall testing for all IC's. This paper describes the present status of Iddq testing along with the essential items and necessary data related to Iddq testing. As part of the introduction, a historical background and discussion is given on why this test method has drawn attention. A section on physical defects with in-depth discussion and examples is used to illustrate why a test method outside the voltage environment is required. Data with additional information from case studies is used to explain the effectiveness of Iddq testing. In Section IV, design issues, design styles, Iddq test vector generation and simulation methods are discussed. The concern of whether Iddq testing will remain useful in deep submicron technologies is addressed (Section V). The use of Iddq testing for reliability screening is described (Section VI). The current measurement methods for Iddq testing are given (Section VII) followed by comments on the economics of Iddq testing (Section VIII). In Section IX pointers to some recent research are given and finally, concluding remarks are given in Section X.

In this paper, we describe the test methodology for embedded cores based system-on-a-chip (SoC) which contains a microprocessor core. First the microprocessor core is tested for correctness of all the instructions and then the computation power of the microprocessor core is used to test the on-chip memories and other cores, A small Iddq test set is also used to detect physical defects. The design features to facilitate Iddq testing are described.

Testing of CoreWare based ASICs is emerging as the most challenging problem of the 1990s. The testing challenge is two fold: first, how to test the embedded cores; and second, how to integrate the test-set of a core with other blocks into ASIC level test-set. Each of these problems is further compounded by the Intellectual Property (IP) protection issue.

A testing method for EEPLA's is presented. The method requires small amount of extra hardware and provides complete fault coverage. This method exploits the fact that each crosspoint can be reprogrammed in EEPLA. To our knowledge, this is the first algorithmic test method applicable to EEPLA's. In the proposed approach, all single and multiple crosspoint faults, stuck-at faults, and bridging faults are detectable. The test set is simple and is easy to derive.>

An analysis and simulation results for multiple token ring networks are presented. The analysis of multiple-ring networks by Q. Yang et al. (1986) is generalized. Closed-form solutions are presented for the token interarrival time and the probability that a station will transmit when a free token arrives, for any packet length or arrival rate, while load is>

The feedback bridging faults are examined in detail for MOS digital circuits. A necessary condition is obtained which needs to be satisfied for oscillations in the circuit. Expression are given to predict the frequency and amplitude of oscillations. It is shown that when a feedback bridging fault does not cause oscillations, it creates an anomalous output. Such faults may not be detected by logic testing: the authors recommend measurement of power supply current to detect such faults in CMOS circuit.>

The operation induced faults in CMOS circuits are discussed. The significance of these faults for high density, small geometry circuits is pointed out. For modeling purposes the effects of these faults are correlated with classical fault models. A conductance fault model is presented to incorporate these faults. A test scheme to detect these faults is suggested which is based on the measurement of supply current. A scheme to generate test patterns for these faults is also outlined.>

CMOS combinational circuits exhibit sequential behavior in the presence of open faults, thus making it necessary to use two pattern tests. Two or multi-pattern sequences may fail to detect CMOS stuck-open faults in the presence of glitches. The available methods for augmenting CMOS gates to test CMOS stuck-open faults, are found to be inadequate in the presence of glitches. A new CMOS testable design is presented. The scheme uses two additional MOSFETs, which convert a CMOS gate to either pseudo nMos or pseudo pMOS gate during testing. The proposed design ensures the detection of stuck-open faults using a single vector during testing

Switch-level models are widely used for fault analysis of MOS digital circuits. Switch-level analysis (SLA) provides significantly more accurate results compared to gate-level models, and also avoids the complexities of circuit-level analysis. The accuracy of SLA is critically examined, and conditions under which SLA may generate incorrect results are specified. Such conditions may occur when the bulk of a transistor is connected to its source. These conditions are especially applicable under certain types of bridging faults. A simple technique is suggested for accurate switch-level modeling under such conditions.>

Bridging faults have been shown to be a major failure mode in VLSI devices. This study examines nMOS and CMOS complex gates in detail for bridging faults. Analysis is carried out using both switch and circuit level models for comparison. It is shown that in most cases, the switch level analysis predicts the correct behavior. A set of conditions are presented, under which the switch level analysis may fail to predict the correct behavior. These conditions can be used for accurate switch level test generation and simulation.