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Remo G. Markgraf

dblp:41/4581 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1992
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware verification and test
0.011992
A hierarchical test pattern generation system based on high-level primitives · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992
Electronic design automation › hardware verification and test › test generation › high-level test generation
hierarchical test generation
0.011992
A hierarchical test pattern generation system based on high-level primitives · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992
Electronic design automation › hardware verification and test
test generation
0.011992
A hierarchical test pattern generation system based on high-level primitives · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992

Methods — techniques the papers use, named apart from their topics

high-level primitives · 0.0fault simulation · 0.0
YearPublicationVenuePosition
1992 A hierarchical test pattern generation system based on high-level primitives
abstract
The authors present an extension of the automatic test pattern generation system SOCRATES to a hierarchical test pattern generation system for combinational and scan-based circuits. The proposed system is based on predefined high-level primitives, e.g., multiplexers and adders. The exploitation of high-level primitives leads to significant improvements in implication, unique sensitization, and multiple backtrace, all of which play a key role in the efficiency of any automatic test pattern generation (ATG) system. In order to perform deterministic ATG and fault simulation for internal faults of high-level primitives, the high-level primitives are dynamically expanded to their gate-level realization. A number of experimental results, achieved on circuits with several tens of thousands of primitives, demonstrate the efficiency of the proposed approach in terms of CPU time, fault coverage, and memory requirements.>
Thomas M. Sarfert, Remo G. Markgraf, Michael H. Schulz, Erwin Trischler
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
1989 Hierarchical Test Pattern Generation Based on High-Level Primitives
abstract
It is demonstrated that the exploitation of high-level primitives (HLPs) and, in particular, of the knowledge concerning their function in ATPG (automatic test pattern generation) leads to significant improvements in implication, unique sensitization, and multiple backtrace. Motivated by this observation and the necessity of covering all faults inside HLPs, the authors present the extension of the ATPG system SOCRATES to hierarchical test pattern generation, which is based upon HLPs and the strategy of dynamically expanding the HLPs to their gate-level realization, at most one at a time. Experimental results have substantiated that the proposed approach performs significantly better in terms of CPU time, elapsed time, fault coverage, and memory requirements than a gate-level ATPG algorithm. It is expected that the extended SOCRATES algorithm will be capable of coping with circuits consisting of 100000 gates and more within reasonable times, even in a workstation environment.>
Thomas M. Sarfert, Remo G. Markgraf, Erwin Trischler, Michael H. Schulz
ITC2