Demo Data from VLDB 2026 / reviewers in the wild / expert
Krishna B. Rajan
dblp:41/5153
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 1996
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
hardware verification and test |
0.0 | 1 | 1992 | Freeze!: A New Approach for Testing Sequential Circuits · DAC 1992 |
Electronic design automation › hardware verification and test
sequential circuit testing |
0.0 | 1 | 1992 | Freeze!: A New Approach for Testing Sequential Circuits · DAC 1992 |
Electronic design automation › hardware verification and test
test generation |
0.0 | 1 | 1992 | Freeze!: A New Approach for Testing Sequential Circuits · DAC 1992 |
Methods — techniques the papers use, named apart from their topics
freeze-based test generation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1996 | Increasing testability by clock transformation (getting rid of those darn states)abstractWe provide a new answer to the fundamental question "Why is sequential test generation so difficult?" the presence of darn (Difficult And Really Needed) states. A darn state is both difficult to reach and required to detect some faults. We introduce a method for identifying darn stares, along with a technique to measure their detrimental effect on the fault coverage. Darn states are the result of detrimental correlation between flip-flops (FFs) sharing the same clock. We propose a novel DFT technique in which FFs are partitioned into different groups having independent clocks during resting. The goal of partitioning is to increase the fault coverage by transforming darn states into easy-to-reach states. The proposed DFT has small area overhead and no performance penalty. Krishna B. Rajan, David E. Long, Miron Abramovici |
VTS | 1 |
| 1992 | Freeze!: A New Approach for Testing Sequential Circuits
Miron Abramovici, Krishna B. Rajan, David T. Miller |
DAC | 2 |