Demo Data from VLDB 2026 / reviewers in the wild / expert
Rhonda Kay Gaede
dblp:41/5398
· DBLP profile ↗
5ranked-venue papers
2as first author
0since 2021 · last 2000
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-authorSoftware engineering, systems software and programming languages · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Parallel and multicore computing · 66% Interconnection networks and networks-on-chip · 22% Electronic design automation · 12% |
Topics — the 7 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Parallel and multicore computing › synchronization
barrier synchronization |
0.0 | 1 | 2000 | An Optical Bus-Based Distributed Dynamic Barrier Mechanism · IEEE Trans. Computers 2000 |
Parallel and multicore computing › synchronization
distributed barrier |
0.0 | 1 | 2000 | An Optical Bus-Based Distributed Dynamic Barrier Mechanism · IEEE Trans. Computers 2000 |
Interconnection networks and networks-on-chip
optical interconnection networks |
0.0 | 1 | 2000 | An Optical Bus-Based Distributed Dynamic Barrier Mechanism · IEEE Trans. Computers 2000 |
Parallel and multicore computing › synchronization
synchronization mechanisms |
0.0 | 1 | 2000 | An Optical Bus-Based Distributed Dynamic Barrier Mechanism · IEEE Trans. Computers 2000 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 1988 | CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology · DAC 1988 |
Electronic design automation › hardware verification and test › test generation
parallel test generation |
0.0 | 1 | 1988 | CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology · DAC 1988 |
Electronic design automation › hardware verification and test
test generation |
0.0 | 1 | 1988 | CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology · DAC 1988 |
Methods — techniques the papers use, named apart from their topics
optical bus · 0.0broadcast-based synchronization · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2000 | A demonstration of repeatable, non-intrusive measurement of program performance and compiler optimization in Linux using IN-TuneabstractCollecting accurate program metrics is often complicated by environmental artifacts such as operating system workload, cache operation, and processor configuration. This paper demonstrates the ability of the IN-Tune system to make accurate and repeatable measurements of program metrics by analyzing the computational workload of programs in the SPEC95 benchmark suite. It shows that metrics which are characteristic of program performance can be collected in both lightly loaded and heavily loaded environments without corruption. The IN-Tune system accomplishes this by creating unique ‘virtual performance registers’ for each process or kernel thread monitored on an Intel processor. Further, this paper investigates the effect optimization has on the performance of the benchmarks. The results clearly show improvements in the quality of code generated by the compiler when optimizations are performed and that, whereas measurements of time can be misleading, the IN-Tune measurements are not. Copyright © 2000 John Wiley & Sons, Ltd. William E. Cohen, Rhonda Kay Gaede, Jeremy B. Rodgers |
Softw. Pract. Exp. | 2 |
| 2000 | An Optical Bus-Based Distributed Dynamic Barrier MechanismabstractBarrier synchronization is a useful parallel programming construct for ensuring that all processors are at a particular location in the code before any processor is allowed to continue. Barrier synchronization is integral to programming models such as the Bulk Synchronous Parallel model. Specialized hardware is often used to improve the performance of a barrier synchronization operation. With continued improvement in processor performance, more efficient synchronization mechanisms are required to counter the rising relative cost of synchronization operations. A high-speed, distributed barrier synchronization mechanism has been developed for broadcast-based optical interconnection networks. This mechanism avoids multiple conversions between optical and electrical signals by having each processor locally decide whether the barrier in which it is participating has been satisfied. It also allows arbitrary sized partitions to be built dynamically during the execution of a program. Simulations of the current hardware design estimate that the barrier synchronization requires less than 300 ns for a 128-processor system. William E. Cohen, David W. Hyde, Rhonda Kay Gaede |
IEEE Trans. Computers | 3 |
| 1999 | IN-Tune: An In-Situ Non-Invasive Performance Tuning Tool for Multi-threaded Linux on Symmetric Multiprocessing Pentium WorkstationsabstractThis paper documents the design and implementation of the IN-Tune software tool suite, which enables a user to collect real-time code and hardware profiling information on Intel-based symmetric multiprocessors running the Linux operating system. IN-Tune provides a virtually non-invasive tool for performance analysis and tuning of programs. Unlike other analysis tools, IN-Tune isolates data with respect to individual threads. It also utilizes performance monitoring hardware registers to permit instrumentation of individual threads as they run in-situ, thus collecting data with appropriate considerations for a multiprocessor environment. Data can be sampled using two different mechanisms. First, the user can collect data by making calls to the system upon the occurrence of specific software events. Secondly, data can be collected at a fixed, fine grain (e.g. 1–10 microseconds) interval using either software or hardware interrupts. To allow observation of codes for which source code modification is impractical or impossible, a ‘shell’ task is created which permits monitoring without code modification. Although this work deals with Intel processors and Linux, the widespread availability of performance monitoring registers in modern processors makes this work widely applicable. Copyright © 1999 John Wiley & Sons, Ltd. Jeremy B. Rodgers, Rhonda Kay Gaede, Jeffrey H. Kulick |
Softw. Pract. Exp. | 2 |
| 1988 | CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology
Rhonda Kay Gaede, Don E. Ross, M. Ray Mercer, Kenneth M. Butler |
DAC | 1 |
| 1986 | Calculation of Greatest Lower Bounds Obtainable by the Cutting Algorithm
Rhonda Kay Gaede, M. Ray Mercer, Bill Underwood |
ITC | 1 |