Rachit Agarwal 0001

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54ranked-venue papers
10as first author
24since 2021 · last 2026
0000-0001-6731-9938ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 26 · 2 first-author · 11 since 2021Software engineering, systems software and programming languages · 10 · 6 since 2021Systems, architecture and hardware · 8 · 4 first-author · 2 since 2021Security and privacy · 4 · 3 since 2021Theory of computation · 4 · 2 first-author · 2 since 2021Applied, interdisciplinary, general and emerging computing · 3 · 2 first-author · 1 since 2021Databases, data management, data science and information retrieval · 1
YearPublicationVenuePosition
2026 OptCCL: Scalable Synthesis of Optimal Collective Communication Algorithms
abstract
We present OptCCL, a technique to synthesize collective communication algorithms that are optimal for a given host and network hardware and topology. OptCCL is general: it enables synthesizing optimal algorithms for all existing collectives, for all existing hardware, and even for multiple concurrent collectives sharing host and network resources. And yet, OptCCL is scalable: it synthesizes optimal algorithms for hundreds of GPUs within tens of minutes.
Richard Shapley, Rachit Agarwal 0001, David B. Shmoys
SIGCOMM2
2026 Understanding Host Network Stack Latency
Tianyu Zuo, Jae-Hyun Hwang, Ao Tang, Rachit Agarwal 0001, Qizhe Cai
SIGCOMM4
2024 Harmony: A Congestion-free Datacenter Architecture
Saksham Agarwal, Qizhe Cai, Rachit Agarwal 0001, David B. Shmoys, Amin Vahdat
NSDI3
2024 High-throughput and Flexible Host Networking for Accelerated Computing
Athinagoras Skiadopoulos, Mark Zhao, Qizhe Cai, Saksham Agarwal, Jacob Adelmann, David Ahern, Carlo Contavalli, Michael D. Goldflam, Vitaly Mayatskikh, Raghu Raja, Daniel Walton, Rachit Agarwal 0001, Shrijeet Mukherjee, Christoforos E. Kozyrakis
OSDI13
2024 Incentives in Dominant Resource Fair Allocation Under Dynamic Demands
Giannis Fikioris, Rachit Agarwal 0001, Éva Tardos
SAGT2
2024 Understanding the Host Network
abstract
The host network integrates processor, memory, and peripheral interconnects to enable data transfer within the host. Several recent studies from production datacenters show that contention within the host network can have significant impact on end-to-end application performance. The goal of this paper is to build an in-depth understanding of such contention within the host network.
Midhul Vuppalapati, Saksham Agarwal, Henry Schuh, Baris Kasikci, Arvind Krishnamurthy, Rachit Agarwal 0001
SIGCOMM6
2024 Fast & Safe IO Memory Protection
abstract
IO Memory protection mechanisms prevent malicious and/or buggy IO devices from executing errant transfers into memory. Modern servers achieve this using an IOMMU---IO devices operate on virtual addresses, and IOMMU translates virtual addresses to physical addresses (potentially speeding up translations using a cache called IOTLB) before executing memory transfers. Despite their importance, design of memory protection mechanisms that can provide strong safety properties while achieving high performance has remained elusive. Indeed, recent studies from production datacenters demonstrate that inefficiencies within state-of-the-art memory protection mechanisms result in significant throughput degradation, orders-of-magnitude tail latency inflation, and violation of isolation guarantees.
Benny Rubin, Saksham Agarwal, Qizhe Cai, Rachit Agarwal 0001
SOSP4
2024 Tiered Memory Management: Access Latency is the Key!
abstract
The emergence of tiered memory architectures has led to a renewed interest in memory management. Recent works on tiered memory management innovate on mechanisms for access tracking, page migration, and dynamic page size determination; however, they all use the same page placement algorithm---packing the hottest pages in the default tier (one with the lowest hardware-specified memory access latency). This makes an implicit assumption that, despite serving the hottest pages, the access latency of the default tier is less than that of alternate tiers. This assumption is far from real: it is well-known in the computer architecture community that, in the realistic case of multiple in-flight requests, memory access latency can be significantly larger than the hardware-specified latency. We show that, even under moderate loads, the default tier access latency can inflate to be 2.5× larger than the latency of alternate tiers; and that, under this regime, performance of state-of-the-art memory tiering systems can be 2.3× worse than the optimal.
Midhul Vuppalapati, Rachit Agarwal 0001
SOSP2
2024 Injection Attacks Against End-to-End Encrypted Applications
abstract
We explore an emerging threat model for end-to-end (E2E) encrypted applications: an adversary sends chosen messages to a target client, thereby "injecting" adversarial content into the application state. Such state is subsequently encrypted and synchronized to an adversarially-visible storage. By observing the lengths of the resulting cloud-stored cipher-texts, the attacker backs out confidential information.We investigate this injection threat model in the context of state-of-the-art encrypted messaging applications that support E2E encrypted backups. We show proof-of-concept attacks that can recover information about E2E encrypted messages or attachments sent via WhatsApp, assuming the ability to compromise the target user’s Google or Apple account (which gives access to encrypted backups). We also show weaknesses in Signal’s encrypted backup design that would allow injection attacks to infer metadata including a target user’s number of contacts and conversations, should the adversary somehow obtain access to the user’s encrypted Signal backup.While we do not believe our results should be of immediate concern for users of these messaging applications, our results do suggest that more work is needed to build tools that enjoy strong E2E security guarantees.
Andrés Fábrega, Carolina Ortega Pérez, Armin Namavari, Ben Nassi, Rachit Agarwal 0001, Thomas Ristenpart
SP5
2024 Exploiting Leakage in Password Managers via Injection Attacks
Andrés Fábrega, Armin Namavari, Rachit Agarwal 0001, Ben Nassi, Thomas Ristenpart
USENIX Security Symposium3
2024 Length Leakage in Oblivious Data Access Mechanisms
Grace Jia, Rachit Agarwal 0001, Anurag Khandelwal
USENIX Security Symposium2
2023 Formal Methods for Network Performance Analysis
Mina Tahmasbi Arashloo, Ryan Beckett, Rachit Agarwal 0001
NSDI3
2023 Karma: Resource Allocation for Dynamic Demands
Midhul Vuppalapati, Giannis Fikioris, Rachit Agarwal 0001, Asaf Cidon, Anurag Khandelwal, Éva Tardos
OSDI3
2023 Host Congestion Control
abstract
The conventional wisdom in systems and networking communities is that congestion happens primarily within the network fabric. However, adoption of high-bandwidth access links and relatively stagnant technology trends for resources within hosts have led to emergence of host congestion---that is, congestion within the host network that enables data exchange between NIC and CPU/memory. Such host congestion alters the many assumptions entrenched within decades of research and practice of congestion control.
Saksham Agarwal, Arvind Krishnamurthy, Rachit Agarwal 0001
SIGCOMM3
2022 Jiffy: elastic far-memory for stateful serverless analytics
abstract
Stateful serverless analytics can be enabled using a remote memory system for inter-task communication, and for storing and exchanging intermediate data. However, existing systems allocate memory resources at job granularity---jobs specify their memory demands at the time of the submission; and, the system allocates memory equal to the job's demand for the entirety of its lifetime. This leads to resource underutilization and/or performance degradation when intermediate data sizes vary during job execution.
Anurag Khandelwal, Yupeng Tang, Rachit Agarwal 0001, Aditya Akella, Ion Stoica
EuroSys3
2022 Understanding host interconnect congestion
abstract
We present evidence and characterization of host congestion in production clusters: adoption of high-bandwidth access links leading to emergence of bottlenecks within the host interconnect (NIC-to-CPU data path). We demonstrate that contention on existing IO memory management units and/or the memory subsystem can significantly reduce the available NIC-to-CPU bandwidth, resulting in hundreds of microseconds of queueing delays and eventual packet drops at hosts (even when running a state-of-the-art congestion control protocol that accounts for CPU-induced host congestion). We also discuss implications of host interconnect congestion to design of future host architecture, network stacks and network protocols.
Saksham Agarwal, Rachit Agarwal 0001, Behnam Montazeri, Masoud Moshref, Khaled Elmeleegy, Luigi Rizzo, Marc de Kruijf, Gautam Kumar 0001, Sylvia Ratnasamy, David E. Culler, Amin Vahdat
HotNets2
2022 SHORTSTACK: Distributed, Fault-tolerant, Oblivious Data Access
Midhul Vuppalapati, Kushal Babel, Anurag Khandelwal, Rachit Agarwal 0001
OSDI4
2022 From Switch Scheduling to Datacenter Scheduling: Matching-Coordinated Greed is Good
abstract
Packet scheduling over a switch (interconnect) fabric is a wellstudied problem in distributed computing, with known near-optimal distributed bipartite matching based protocols.
Rachit Agarwal 0001, Shijin Rajakrishnan, David B. Shmoys
PODC1
2022 dcPIM: near-optimal proactive datacenter transport
abstract
Datacenter Parallel Iterative Matching (dcPIM) is a proactive data-center transport design that simultaneously achieves near-optimal tail latency for short flows and near-optimal network utilization, without requiring any specialized network hardware.
Qizhe Cai, Mina Tahmasbi Arashloo, Rachit Agarwal 0001
SIGCOMM3
2022 Towards μs tail latency and terabit ethernet: disaggregating the host network stack
abstract
Dedicated, tightly integrated, and static packet processing pipelines in today's most widely deployed network stacks preclude them from fully exploiting capabilities of modern hardware.
Qizhe Cai, Midhul Vuppalapati, Jae-Hyun Hwang, Christoforos E. Kozyrakis, Rachit Agarwal 0001
SIGCOMM5
2022 Optimal oblivious reconfigurable networks
abstract
Oblivious routing has a long history in both the theory and practice of networking. In this work we initiate the formal study of oblivious routing in the context of reconfigurable networks, a new architecture that has recently come to the fore in datacenter networking. These networks allow a rapidly changing bounded-degree pattern of interconnections between nodes, but the network topology and the selection of routing paths must both be oblivious to the traffic demand matrix. Our focus is on the trade-off between maximizing throughput and minimizing latency in these networks. For every constant throughput rate, we characterize (up to a constant factor) the minimum latency achievable by an oblivious reconfigurable network design that satisfies the given throughput guarantee. The trade-off between these two objectives turns out to be surprisingly subtle: the curve depicting it has an unexpected scalloped shape reflecting the fact that load-balancing becomes more difficult when the average length of routing paths is not an integer because equalizing all the path lengths is not possible. The proof of our lower bound uses LP duality to verify that Valiant load balancing is the most efficient oblivious routing scheme when used in combination with an optimally-designed reconfigurable network topology. The proof of our upper bound uses an algebraic construction in which the network nodes are identified with vectors over a finite field, the network topology is described by either the elementary basis or a sequence of Vandermonde matrices, and routing paths are constructed by selecting columns of these matrices to yield the appropriate mixture of path lengths within the shortest possible time interval.
Daniel Amir, Tegan Wilson, Vishal Shrivastav, Hakim Weatherspoon, Robert D. Kleinberg, Rachit Agarwal 0001
STOC6
2021 CodedBulk: Inter-Datacenter Bulk Transfers using Network Coding
Shih-Hao Tseng, Saksham Agarwal, Rachit Agarwal 0001, Hitesh Ballani, Ao Tang
NSDI3
2021 Rearchitecting Linux Storage Stack for µs Latency and High Throughput
Jae-Hyun Hwang, Midhul Vuppalapati, Simon Peter 0001, Rachit Agarwal 0001
OSDI4
2021 Understanding host network stack overheads
abstract
Traditional end-host network stacks are struggling to keep up with rapidly increasing datacenter access link bandwidths due to their unsustainable CPU overheads. Motivated by this, our community is exploring a multitude of solutions for future network stacks: from Linux kernel optimizations to partial hardware offload to clean-slate userspace stacks to specialized host network hardware. The design space explored by these solutions would benefit from a detailed understanding of CPU inefficiencies in existing network stacks.
Qizhe Cai, Shubham Chaudhary 0004, Midhul Vuppalapati, Jae-Hyun Hwang, Rachit Agarwal 0001
SIGCOMM5
2020 TCP ≈ RDMA: CPU-efficient Remote Storage Access with i10
Jae-Hyun Hwang, Qizhe Cai, Ao Tang, Rachit Agarwal 0001
NSDI4
2020 Building An Elastic Query Engine on Disaggregated Storage
Midhul Vuppalapati, Justin Miron, Rachit Agarwal 0001, Dan Truong, Ashish Motivala, Thierry Cruanes
NSDI3
2020 Pancake: Frequency Smoothing for Encrypted Data Stores
Paul Grubbs, Anurag Khandelwal, Marie-Sarah Lacharité, Lloyd Brown, Lucy Li, Rachit Agarwal 0001, Thomas Ristenpart
USENIX Security Symposium6
2019 Confluo: Distributed Monitoring and Diagnosis Stack for High-speed Networks
Anurag Khandelwal, Rachit Agarwal 0001, Ion Stoica
NSDI2
2019 Shoal: A Network Architecture for Disaggregated Racks
Vishal Shrivastav, Asaf Valadarsky, Hitesh Ballani, Paolo Costa, Ki Suh Lee, Han Wang 0009, Rachit Agarwal 0001, Hakim Weatherspoon
NSDI7
2018 Distributed Network Monitoring and Debugging with SwitchPointer
Praveen Tammana, Rachit Agarwal 0001, Myungjin Lee
NSDI2
2018 Obladi: Oblivious Serializable Transactions in the Cloud
Natacha Crooks, Matthew Burke 0001, Ethan Cecchetti, Sitar Harel, Rachit Agarwal 0001, Lorenzo Alvisi
OSDI5
2018 Sincronia: near-optimal network design for coflows
abstract
We present Sincronia, a near-optimal network design for coflows that can be implemented on top on any transport layer (for flows) that supports priority scheduling. Sincronia achieves this using a key technical result --- we show that given a "right" ordering of coflows, any per-flow rate allocation mechanism achieves average coflow completion time within 4X of the optimal as long as (co)flows are prioritized with respect to the ordering.
Saksham Agarwal, Shijin Rajakrishnan, Akshay Narayan 0001, Rachit Agarwal 0001, David B. Shmoys, Amin Vahdat
SIGCOMM4
2017 MiniCrypt: Reconciling Encryption and Compression for Big Data Stores
abstract
We propose MiniCrypt, the first key-value store that reconciles encryption and compression without compromising performance. At the core of MiniCrypt is an observation on data compressibility trends in key-value stores, which enables grouping key-value pairs into small key packs, together with a set of distributed systems techniques for retrieving, updating, merging and splitting encrypted packs. Our evaluation shows that MiniCrypt compresses data by as much as 4 times with respect to the vanilla key-value store, and can increase the server's throughput by up to two orders of magnitude by fitting more data in main memory.
Wenting Zheng, Frank Li 0001, Raluca A. Popa, Ion Stoica, Rachit Agarwal 0001
EuroSys5
2017 ZipG: A Memory-efficient Graph Store for Interactive Queries
abstract
We present ZipG, a distributed memory-efficient graph store for serving interactive graph queries. ZipG achieves memory efficiency by storing the input graph data using a compressed representation. What differentiates ZipG from other graph stores is its ability to execute a wide range of graph queries directly on this compressed representation. ZipG can thus execute a larger fraction of queries in main memory, achieving query interactivity. ZipG exposes a minimal API that is functionally rich enough to implement published functionalities from several industrial graph stores. We demonstrate this by implementing and evaluating graph queries from Facebook TAO, LinkBench, Graph Search and several other workloads on top of ZipG. On a single server with 244GB memory, ZipG executes tens of thousands of queries from these workloads for raw graph data over half a TB; this leads to an order of magnitude (sometimes as much as 23×) higher throughput than Neo4j and Titan. We get similar gains in distributed settings compared to Titan.
Anurag Khandelwal, Zongheng Yang, Evan Ye, Rachit Agarwal 0001, Ion Stoica
SIGMOD Conference4
2016 BlowFish: Dynamic Storage-Performance Tradeoff in Data Stores
Anurag Khandelwal, Rachit Agarwal 0001, Ion Stoica
NSDI2
2016 Universal Packet Scheduling
Radhika Mittal, Rachit Agarwal 0001, Sylvia Ratnasamy, Scott Shenker
NSDI2
2016 Network Requirements for Resource Disaggregation
Peter Xiang Gao, Akshay Narayan 0001, Sagar Karandikar, Sangjin Han, Rachit Agarwal 0001, Sylvia Ratnasamy, Scott Shenker
OSDI6
2016 Simplifying Datacenter Network Debugging with PathDump
Praveen Tammana, Rachit Agarwal 0001, Myungjin Lee
OSDI2
2015 FastLane: making short flows shorter with agile drop notification
abstract
The drive towards richer and more interactive web content places increasingly stringent requirements on datacenter network performance. Applications running atop these networks typically partition an incoming query into multiple subqueries, and generate the final result by aggregating the responses for these subqueries. As a result, a large fraction --- as high as 80% --- of the network flows in such workloads are short and latency-sensitive. The speed with which existing networks respond to packet drops limits their ability to meet high-percentile flow completion time SLOs. Indirect notifications indicating packet drops (e.g., duplicates in an end-to-end acknowledgement sequence) are an important limitation to the agility of response to packet drops.
David Zats, Anand Padmanabha Iyer, Ganesh Ananthanarayanan, Rachit Agarwal 0001, Randy H. Katz, Ion Stoica, Amin Vahdat
SoCC4
2015 pHost: distributed near-optimal datacenter transport over commodity network fabric
abstract
The importance of minimizing flow completion times (FCT) in datacenters has led to a growing literature on new network transport designs. Of particular note is pFabric, a protocol that achieves near-optimal FCTs. However, pFabric's performance comes at the cost of generality, since pFabric requires specialized hardware that embeds a specific scheduling policy within the network fabric, making it hard to meet diverse policy goals. Aiming for generality, the recent Fastpass proposal returns to a design based on commodity network hardware and instead relies on a centralized scheduler. Fastpass achieves generality, but (as we show) loses many of pFabric's performance benefits.
Peter Xiang Gao, Akshay Narayan 0001, Gautam Kumar 0001, Rachit Agarwal 0001, Sylvia Ratnasamy, Scott Shenker
CoNEXT4
2015 Universal Packet Scheduling
abstract
In this paper we address a seemingly simple question: Is there a universal packet scheduling algorithm? More precisely, we analyze (both theoretically and empirically) whether there is a single packet scheduling algorithm that, at a network-wide level, can match the results of any given scheduling algorithm. We find that in general the answer is "no". However, we show theoretically that the classical Least Slack Time First (LSTF) scheduling algorithm comes closest to being universal and demonstrate empirically that LSTF can closely, though not perfectly, replay a wide range of scheduling algorithms in realistic network settings. We then evaluate whether LSTF can be used in practice to meet various network-wide objectives by looking at three popular performance metrics (mean FCT, tail packet delays, and fairness); we find that LSTF performs comparable to the state-of-the-art for each of them.
Radhika Mittal, Rachit Agarwal 0001, Sylvia Ratnasamy, Scott Shenker
HotNets2
2015 Succinct: Enabling Queries on Compressed Data
Rachit Agarwal 0001, Anurag Khandelwal, Ion Stoica
NSDI1
2015 On the Scalability of Routing With Policies
abstract
Today’s ever-growing networks call for routing schemes with sound theoretical scalability guarantees. In this context, a routing scheme is scalable if the amount of memory needed to implement it grows significantly slower than the network size. Unfortunately, theoretical scalability characterizations only exist for shortest path routing, but for general policy routing that current and future networks increasingly rely on, very little understanding is available. In this paper, we attempt to fill this gap. We define a general framework for policy routing, and we study the theoretical scaling properties of three fundamental policy models within this framework. Our most important contributions are the finding that, contrary to shortest path routing, there exist policies that inherently scale well, and a separation between the class of policies that admit compact routing tables and those that do not. Finally, we ask to what extent memory size can be decreased by allowing paths to contain a certain bounded number of policy violations and, surprisingly, we conclude that most unscalable policies remain unscalable under the relaxed model as well.
András Gulyás, Gábor Rétvári, Zalán Heszberger, Rachit Agarwal 0001
IEEE/ACM Trans. Netw.4
2014 The Space-Stretch-Time Tradeoff in Distance Oracles
Rachit Agarwal 0001
ESA1
2013 Brief announcement: a simple stretch 2 distance oracle
abstract
We present a distance oracle that, for weighted graphs with n vertices and m edges, is of size 8n4/3m1/3log2/3n and returns stretch-2 distances in constant time. Our oracle achieves bounds identical to the constant-time stretch-2 oracle of Pǎtraşcu and Roditty, but admits significantly simpler construction and proofs.
Rachit Agarwal 0001, Brighten Godfrey
PODC1
2013 Distance Oracles for Stretch Less Than 2
abstract
We present distance oracles for weighted undirected graphs that return distances of stretch less than 2. For the realistic case of sparse graphs, our distance oracles exhibit a smooth three-way trade-off between space, stretch and query time — a phenomenon that does not occur in dense graphs. In particular, for any positive integer t and for any 1 ≤ α ≤ n, our distance oracle is of size O(m + n2/α) and returns distances of stretch at most in time O((αμ)t), where μ = 2m/n is the average degree of the graph. The query time can be further reduced to O((α + μ)t) at the expense of a small additive stretch.
Rachit Agarwal 0001, Brighten Godfrey
SODA1
2011 Approximate distance queries and compact routing in sparse graphs
abstract
An approximate distance query data structure is a compact representation of a graph, and can be queried to approximate shortest paths between any pair of vertices. Any such data structure that retrieves stretch 2k Ω 1 paths must require space Ω(n1+1/k) for graphs of n nodes. The hard cases that enforce this lower bound are, however, rather dense graphs with average degree Ω(n1/k). We present data structures that, for sparse graphs, substantially break that lower bound barrier at the expense of higher query time. For instance, general graphs require O(n3/2) space and constant query time for stretch 3 paths. For the realistic scenario of a graph with average degree Θ(log n), special cases of our data structures retrieve stretch 2 paths with O(n3/2) space and stretch 3 paths with O̅(n) space, albeit at the cost of O̅(√n) query time. Moreover, supported by large-scale simulations on graphs including the AS-level Internet graph, we argue that our stretch-2 scheme would be simple and efficient to implement as a distributed compact routing protocol.
Rachit Agarwal 0001, Brighten Godfrey, Sariel Har-Peled
INFOCOM1
2011 Combinatorial lower bound for list decoding of codes on finite-field Grassmannian
abstract
Codes constructed as subsets of the projective geometry of a vector space over a finite field have been shown to have applications as random network error correcting codes. If the dimension of each codeword is restricted to a fixed integer, the code forms a subset of a finite-field Grassmannian, or equivalently, a subset of the vertices of the corresponding Grassmannian graph. These codes are referred to as codes on finite-field Grassmannian or more generally as subspace codes. In this paper, we study fundamental limits to list decoding codes on finite-field Grassmannian. By exploiting the algebraic properties of the Grassmannian graph, we derive a new lower bound on the code size for the first relaxation of bounded minimum distance decoding, that is, when the worst-case list size is restricted to two. We show that, even for small finite field size and code parameters, codes on finite-field Grassmannian admit significant improvements in code rate when compared to bounded minimum distance decoding.
Rachit Agarwal 0001
ISIT1
2011 Debugging the data plane with anteater
abstract
Diagnosing problems in networks is a time-consuming and error-prone process. Existing tools to assist operators primarily focus on analyzing control plane configuration. Configuration analysis is limited in that it cannot find bugs in router software, and is harder to generalize across protocols since it must model complex configuration languages and dynamic protocol behavior.
Haohui Mai, Ahmed Khurshid, Rachit Agarwal 0001, Matthew Caesar 0001, Brighten Godfrey, Samuel T. King
SIGCOMM3
2011 Slick packets
abstract
Source-controlled routing has been proposed as a way to improve flexibility of future network architectures, as well as simplifying the data plane. However, if a packet specifies its path, this precludes fast local re-routing within the network. We propose SlickPackets, a novel solution that allows packets to slip around failures by specifying alternate paths in their headers, in the form of compactly-encoded directed acyclic graphs. We show that this can be accomplished with reasonably small packet headers for real network topologies, and results in responsiveness to failures that is competitive with past approaches that require much more state within the network. Our approach thus enables fast failure response while preserving the benefits of source-controlled routing.
Giang T. K. Nguyen, Rachit Agarwal 0001, Junda Liu, Matthew Caesar 0001, Brighten Godfrey, Scott Shenker
SIGMETRICS2
2010 Guaranteeing BGP Stability with a Few Extra Paths
abstract
Policy autonomy exercised by Autonomous Systems (ASes) on the Internet can result in persistent oscillations in Border Gateway Protocol, the Internet's inter-domain routing protocol. Current solutions either rely on globally consistent policy assignments, or require significant deviations from locally assigned policies, resulting in significant loss of autonomy of ASes. In this paper, we take a different approach that guarantees stability with less restrictive policies. Namely, we propose multipath routing to find a better trade-off between AS policy autonomy and system stability. We design an algorithm, STABLE PATH(S) ASSIGNMENT (SPA), that provably detects persistent oscillations and eliminates these oscillations by assigning multiple paths to some ASes in the network. Such an assignment allows each AS to use its most-preferred available path, while requiring very few ASes to carry transit traffic along additional paths in order to break oscillations. We design a distributed protocol for SPA and present tight bounds on the number of paths assigned to the ASes in the network. Using simulations on the AS graph, we show that in presence of oscillations, SPA assigns at most two paths to any AS in the network (in 99.9% of the instances), with an extremely small fraction of ASes assigned the extra path.
Rachit Agarwal 0001, Virajith Jalaparti, Matthew Caesar 0001, Brighten Godfrey
ICDCS1
2010 When Watchdog Meets Coding
abstract
We consider the problem of misbehavior detection in wireless networks. A commonly adopted approach is to exploit the broadcast nature of the wireless medium, where nodes monitor their downstream neighbors locally using overheard messages. We call such nodes the Watchdogs. We propose a lightweight misbehavior detection scheme which integrates the idea of watchdogs and error detection coding. We show that even if the watchdog can only observe a fraction of packets, by choosing the error detection code properly, an attacker can be detected with high probability while achieving throughput arbitrarily close to optimal. Such properties reduce the incentive for the attacker to attack. We then consider the problem of locating the misbehaving node and propose a simple protocol, which locates the misbehaving node with high probability. The protocol requires exactly two watchdogs per unreliable relay node.
Guanfeng Liang, Rachit Agarwal 0001, Nitin H. Vaidya
INFOCOM2
2007 A Parallel Architecture for Hermitian Decoders: Satisfying Resource and Throughput Constraints
abstract
Hermitian codes offer desirable properties such as large code lengths, good error-correction at high code rates, etc. The main problem in making Hermitian codes practical is to find a way of performing the required computations in a fast and memory efficient way so as to satisfy resource and throughput constraints imposed by the systems. The paper presents some architecture for Hermitian decoders which enhance their applicability in communication systems. Formulae and architectures for gap detection and address generation unit for satisfying memory constraints have been presented, which amount to 50% savings in storage area and 10% savings in the number of clock cycles reported in literature. A semi-parallel architecture is proposed as a solution to the latency and resource requirements tradeoff, which improves the throughput about q times compared to the word-serial architecture at an expense of some q times more adders, multipliers and simple multiplexers, where the code is defined over GF(q2). For a t error correcting code, the resource load of the parallel architectures is about gamma(t/q + (q-3)/4)( t/q + (q-3)/4 + 1) times this architecture, where gamma is the resource requirement ratio of a multiplier and an inverter
Rachit Agarwal 0001, Emanuel M. Popovici, Brendan O'Flynn, Michael E. O'Sullivan
ISCAS1
2007 A Low Complexity Algorithm and Architecture for Systematic Encoding of Hermitian Codes
abstract
We present an algorithm for systematic encoding of Hermitian codes. For a Hermitian code defined overGF(q2), the proposed algorithm achieves a run time complexity ofO(q2) and is suitable for VLSI implementation. The encoder architecture uses as main blocksqvarying-rate Reed-Solomon encoders and achieves a space complexity ofO(q2) in terms of finite field multipliers and memory elements.
Rachit Agarwal 0001, Ralf Koetter, Emanuel M. Popovici
ISIT1