The number of cores in embedded systems is continuously growing, supporting increasingly complex concurrent applications. In order to verify that the systems comply specification requirements during the design process, fast simulations and performance analysis tools are required. These simulation frameworks typically use virtualization or host-compiled simulation techniques. On one hand, current host compiler simulators normally offer fast simulations, but they do not exploit host parallelism capacity. On the other hand, some virtual emulation frameworks take advantage of host parallelization, but they do not achieve simulations as fast as native (host-compiled) simulators because of the dynamic binary translation. This paper proposes a parallel host-compiled simulation methodology that aims to make an efficient use of multi-core host platforms. The performance of the proposed technique has been evaluated with the PARSEC benchmark suite [10]. The evaluation also includes comparisons with native execution and other parallel simulation tools. Results demonstrate that the proposed technique reduces simulation time and provide fast estimations of embedded SW code.

Nowadays, the verification of systems has grown to dominate the cost of electronic system design, often with limited success, as designs continue to be released with latent bugs. The International Technology Roadmap for Semiconductors (ITRS) affirms in the report of 2005 that for the most complex designs, verification engineers outnumber designers with this ratio reaching two or three to one. Assertion-based verification (ABV) is a promising methodology to confront the growing problem of system design verification (Yeung and Larsen, 2005). Key aspects in increasing the scalability of formal and semi-formal verification techniques are the role of the solver and the level of abstraction of the system description. Several assertion checking techniques based on nonlinear solvers have been proposed to verify assertions in behavioral level system descriptions. These techniques are very efficient with data dominated designs (for example digital filters) but they have a lot of problems with control dominated designs in which the variables have a small set of possible values (typically two, 0 and 1). This paper presents several techniques that allow the use of a commercial nonlinear solver to check assertions in control dominated design. And it studies in depth some techniques that allow the transformation of the behavioral level system description into a set of polynomial inequalities that efficiently model control dominated designs. The goal of the verification methodology is maximizing a nonlinear equation (the assertion equation in this paper) while satisfying a set of non-linear constraints (polynomial inequalities) that model conditional statements and discontinuous functions in this work. The commercial solver LINDO is an example of a global non-linear solver and it has been used in this work. In order to validate the proposed technique, the example 'MPEG system decoder' used by (Mitchel et al., 1997) for HW verification is selected. The system decoder is composed of several modules, completely decoupled behaviorally amongst themselves. The verification can be done individually for each module. The property "EF (stop = "1") (LTL nomenclature) has to be verified to guarantee that the composite design will work. The table shows the results. These components are control dominated designs with very few data operations. The second column (non-linear) shows the CPU time of the proposed technique, while the third column presents the time of a commercial integer solver. It can be shown that the proposed technique provides similar results to an integer solver with pure control descriptions

Verification has become the major bottleneck of the design process. According to the latest report of the International Technology Roadmap for Semiconductors, the challenge is to develop new design-for-verifiability techniques and verification methods for higher levels of abstraction. Several design-for-verifiability methodologies (DFV) have been proposed and assertion-based verification (ABV) is one of the most promising. In order to automatically verify assertions at the higher abstraction levels, it is necessary to improve the performances and capabilities of current constraint solvers. This paper presents a new technique based on nonlinear solvers that automatically checks assertions in behavioral descriptions of hardware systems. These descriptions are modeled with a set of integer polynomial inequalities. The technique provides better results than SAT solvers and it is applied to real designs, such as Viterbi decoders or vocoder digital filters.

As the latest version of the International Technology Roadmap for Semiconductor (ITRS) highlights, verification has become the dominant cost of the electronic system design process. Although advances in formal methods have improved some aspects of the task, software simulation remains the primary method of functional verification. Traditionally, heuristic coverage metrics have been used to evaluate the simulation-based verification process. This coverage-based approach has a very serious disadvantage: the metrics have no formal meaning and so there is no direct correlation between classes of bugs and coverage metrics. The main goal of this paper is to explore methods that provide a formal meaning to branch coverage with random test benches. The methods are based on polynomial models of the system under verification and they are independent of a particular fault model.

At-speed testing of GHz processors using external testers may not be technically and economically feasible. Hence, there is an emerging need for low-cost, high-quality self-test methodologies, which can be used by processors to test themselves at-speed. Currently, Built-In Self-Test (BIST) is the primary self-test methodology available and is widely used for testing embedded memory cores. In this paper, we report our experiences in applying a commercial BIST methodology to two processor cores and analyze the problems associated with the current hardware-based BIST methodologies. We propose a new software-based self-testing methodology for processors, which uses a software tester embedded in the processor memory as a vehicle for applying structural tests. The software tester consists of programs for test generation and test application. Prior to the test, structural tests are prepared for processor components in the form of self-test signatures. During the process of self-test, the test generation program expands the self-test signatures into test sets, and the test application program applies the tests to the components-under-test at the speed of the processor. Application of the novel software-based self-test method demonstrates its significant cost/fault coverage benefits and its ability to apply at-speed test while alleviating the need for high-speed testers.

Gate level fault simulation has been a typical step in the ASIC design process but it cannot be used for real hardware/software systems in which there are multiple boards and chips, several test strategies, complex embedded systems in ASICs and different test procedures (hardware test pattern generation, software programs for hardware tests, etc.). This paper proposes a new methodology bared on VHDL which covers the new fault simulation demands of real digital systems.