Most existing image captioning evaluation metrics focus on assigning a single numerical score to a caption by comparing it with reference captions.However, these methods do not provide an explanation for the assigned score.Moreover, reference captions are expensive to acquire.In this paper, we propose FLEUR 1 , an explainable reference-free metric to introduce explainability into image captioning evaluation metrics.By leveraging a large multimodal model, FLEUR can evaluate the caption against the image without the need for reference captions, and provide the explanation for the assigned score.We introduce score smoothing to align as closely as possible with human judgment and to be robust to user-defined grading criteria.FLEUR achieves high correlations with human judgment across various image captioning evaluation benchmarks and reaches state-of-the-art results on Flickr8k-CF, COMPOSITE, and Pascal-50S within the domain of reference-free evaluation metrics.Our source code and results are publicly available at: https://github.com/ Yebin46/FLEUR. * Equal contribution. Correspondence to: Myungjoo Kang 1We choose a word in French that means 'flower', in line with other French-named evaluation metrics.2 A reference caption refers to the human-annotated caption for an image.A candidate caption refers to the caption that is to be evaluated. Score: 0.02418The caption does not accurately describe the image.The image shows a boy walking out of the ocean water on the beach, holding a paddle.There is no dog or any object in the dog's mouth in the image.The caption is unrelated to the actual content of the image, which is why it receives a low score.A black dog is coming out of the ocean water on the beach with something in its mouth.BLEU-4: 0.25 ROUGE-L: 0.

Owing to increasing demand of faster and larger DRAM system, the DRAM system accounts for a large portion of the total power consumption of computing systems. As memory traffic and DRAM bandwidth grow, the row activation and I/O power consumptions are becoming major contributors to total DRAM power consumption. Thus, reducing row activation and I/O power consumptions has big potential for improving the power and energy efficiency of the computing systems. To this end, we propose a partial row activation scheme for memory writes, in which DRAM is rearchitected to mitigate row overfetching problem of modern DRAMs and to reduce row activation power consumption. In addition, accompanying I/O power consumption in memory writes is also reduced by transferring only a part of cache line data that must be written to partially opened rows. In our proposed scheme, partial rows ranging from a one-eighth row to a full row can be activated to minimize row activation granularity for memory writes and the full bandwidth of the conventional DRAM can be maintained for memory reads. Our partial row activation scheme is shown to reduce total DRAM power consumption by up to 32% and 23% on average, which outperforms previously proposed schemes in DRAM power saving with almost no performance loss.

DRAMs are one of the main players of the computer system energy consumption. Thus, reducing DRAM energy consumption has a big potential to save the entire system energy consumption. Because the standby power consumption of DRAM is significant, modern DRAMs provide low-power modes for reducing idle energy consumption. However, the use of low-power modes can degrade the performance because state transitions to/from low-power states involve a time penalty. To effectively utilize low-power modes, we propose DRAM rank-aware memory scheduling schemes. One scheme utilizes a prioritized cache block replacement method considering the power states of DRAM ranks to select victim blocks for the late level cache. Through this scheme, DRAM traffic and the number of state transitions of DRAM ranks can be reduced. The other scheme utilizes the memory controller by controlling write traffic to DRAM with the awareness of the DRAM rank states. DRAM rank idle times and state transitions can be reduced by this scheme. Our proposed schemes are shown to reduce DRAM energy consumption by 15.2 percent on average.

DRAM is one of the main sources of energy consumption in computer systems. Thus, reducing the energy consumption of DRAM can prolong the lifetime of battery-operated embedded/mobile systems. To this end, we propose a DRAM energy-aware prefetching scheme to increase row buffer hits and idle periods of DRAM by clustering its accesses. Although prefetching schemes have traditionally been used to improve the system performance, utilizing them for the energy conservation of DRAM has yet to be investigated. For such energy conservation, our scheme accurately predicts and clusters potential future DRAM accesses. Clustered DRAM accesses exploit a popular first-ready first-come first-serve memory request scheduling and a power-down mode of DRAM more effectively; the probability of row buffer hits and idle periods is significantly increased by our clustering scheme. As a result, large amounts of row activation and idle energy consumption, which are major energy consumption factors in modern DRAM, can be saved. Our prefetching-based memory traffic-clustering scheme was shown to reduce the power and energy consumption of DRAM and improve its performance by an average of 0.2%, 28.9%, and 15.7%, respectively, for memory-intensive programs.

DRAMs are one of the main players of computer system energy consumption due to their large capacities and frequent accesses. Consequently, many schemes have been proposed to reduce DRAM power/energy consumption. Some of them propose new DRAM system and chip organizations, which are effective in reducing power consumption but intrusive. In contrast, we minimize DRAM write accesses at chip level with minimal modification of the conventional DRAM system organization and small addition to caches. When all data going to the same DRAM chips are not modified, the chips are not accessed. Consequently, chips are accessed selectively in our scheme while all chips are accessed simultaneously in the conventional DRAM system. Our chip-based selective DRAM write scheme is shown to reduce DRAM power and energy consumptions by 17% and 14%, respectively, on average. The overheads of our scheme are small in terms of performance, area, and energy consumption.

Modern DRAMs provide multiple low-power states to save their energy consumption during idle times. The use of low-power states, however, can cause performance degradation because state transitions from low-power states to an active state incur time penalty. To effectively utilize the low-power states, we propose DRAM power-aware rank scheduling schemes applied to the last-level cache and the memory controller. Our scheme utilizing the last-level cache reduces write requests to DRAM and the state transitions by replacing cache blocks based on their dirty states and DRAM rank power states. Our scheme utilizing the memory controller decreases the state transitions with rank power state-aware batch writes. With the second scheme, the states transitions are reduced by 21.2%, on average. Consequently DRAM energy consumption is reduced by 11.2%, on average, with no performance loss.

DRAMs consume a large portion of total system energy consumption. Thus, reducing DRAM energy consumption is able to prolong the lifetime of battery-operated embedded/portable systems. To this end, we propose DRAM energy-aware data prefetching scheme to lengthen DRAM idle periods by clustering DRAM accesses. Low-power modes of DRAMs can better exploit longer idle times. We performed experiments with a cycle-accurate simulator with built-in DRAM power model. The experimental results show that our proposed DRAM-aware prefetching is effective in reducing DRAM energy consumption. Up to 77% and average 59% of DRAM energy consumption is saved.

Though tag bits in the data caches are vulnerable to transient errors, few effort has been made to reduce their vulnerability. In this paper, we propose to exploit prevalent same tag bits to improve error protection capability of the tag bits in the data caches. When data are fetched from the main memory, it is checked if adjacent cache lines have the same tag bits as those of the data fetched. This similarity information is stored in the data caches as extra bits to be used later. When an error is detected in the tag bits, the similarity information is used to recover from the error in the tag bits. The proposed scheme has small area, energy, and performance overheads with error protection coverage of 97.9% on average. In contrast, the previously proposed In-Cache Replication scheme is shown to incur large performance and energy overheads.