Real number models, which are computationally efficient analog functional models, are now indispensable in verifying complex mixed-signal systems on chip (SoCs); yet, creating and validating these models remain difficult. To remove this problem, we created a framework for building analog functional model templates. Each template covers a class of circuits (e.g., oscillators or amplifiers) and can generate functional models for any implementation of this circuit class, regardless of pin configurations, circuit topologies, and process technologies/corners. This ability to cover many implementations with one template allows one to create a “standard model template” library that covers all the basic analog building blocks used in mixed-signal SoCs. Like a digital standard cell library, this template library only contains the low-level building blocks. Models for more complex systems, such as a phase-locked loop, are constructed using a number of these models. Our template library also contains validation routines for each of the models, measuring the key performance parameters of the modeled function. These routines can also be used to drive the circuit-level implementation of this function, making it easy to update the parameters of the functional models to match their circuit implementations. We demonstrate the utility of our template library on several mixed-signal IPs integrated into an SoC. Using the proposed framework, designers can easily generate a working model of an analog functional block in a second and thus construct a complete mixed-signal IP model for the design exploration in less than a couple of hours, while it typically needs a few days when the models are manually written. The regeneration of the models to reflect the behaviors of real implementations can be seamlessly done in less half a day from the same template library. In addition to the vast improvement in model creation speed, the generated model from the template library is less error-prone by archiving designer's experience from previous mistakes to the template library.

In this paper, we propose an architecture for FPGA emulation of mixed-signal systems that achieves high accuracy at a high throughput. We represent the analog output of a block as a superposition of step responses to changes in its analog input, and the output is evaluated only when needed by the digital subsystem. Our architecture is therefore intended for digitally-driven systems; that is, those in which the inputs of analog dynamical blocks change only on digital clock edges. We implemented a high-speed link transceiver design using the proposed architecture on a Xilinx FPGA. This design demonstrates how our approach breaks the link between simulation rate and time resolution that is characteristic of prior approaches. The emulator is flexible, allowing for the real-time adjustment of analog dynamics, clock jitter, and various design parameters. We demonstrate that our architecture achieves 1% accuracy while running 3 orders of magnitude faster than a comparable high-performance CPU simulation.

As analog and digital circuits have become more intertwined, we need to create a validation approach that handles both circuit types gracefully. This paper proposes a model-first approach, where one creates functional models of the analog blocks that will work in a HDL simulator, and then uses these models in the same way as HDL models are used for other standard cells: they are used in the full system validation, and the underlying implementations are validated to ensure they meet this specification. While creating functional models for the analog blocks might seem difficult, almost all analog blocks can be modeled as linear systems and we use this property to help create the required functional model.

This paper presents an approach to generate test vectors to characterize analog/mixed-signal circuits and its application to check the correspondence between a circuit and its HDL functional model. Interestingly, the abstract behavior of most analog circuits is a linear system, but sometimes only when viewed through a transformation of variables. When linearity holds, validation for the consistency between a circuit and a model can be efficiently performed with a small set of test vectors that grows linearly with the number of analog inputs. The linear abstraction for analog circuits also helps us distinguish different types of analog and digital I/O ports and verify their consistency effectively. We demonstrate the implemented tool by comparing a simple serial link receiver against its functional model.