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Sitian Lu

dblp:413/5834 · DBLP profile ↗
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2ranked-venue papers
0as first author
2since 2021 · last 2026
0009-0002-3469-7136ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021Databases, data management, data science and information retrieval · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Distributed systems · 45% Parallel and multicore computing · 44% High-performance computing · 10%
Artificial intelligence
1 paper
Efficient and distributed learning · 67% Graph learning · 33%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Distributed systems
fault tolerance
1.012026
ResiHP: Taming LLM Training Failures with Dynamic Hybrid Parallelism · HPDC 2026
Parallel and multicore computing › parallelization strategies
hybrid parallelism
1.012026
ResiHP: Taming LLM Training Failures with Dynamic Hybrid Parallelism · HPDC 2026
Machine learning › Graph learning › graph neural network
dynamic graph neural network
0.912025
PipeTGL: (Near) Zero Bubble Memory-based Temporal Graph Neural Network Training via Pipeline Optimization · Proc. VLDB Endow. 2025
Machine learning › Efficient and distributed learning › distributed training › parallelization › parallel training
multi-GPU training
0.912025
PipeTGL: (Near) Zero Bubble Memory-based Temporal Graph Neural Network Training via Pipeline Optimization · Proc. VLDB Endow. 2025
Machine learning › Efficient and distributed learning › distributed training › model parallelism
pipeline parallelism
0.912025
PipeTGL: (Near) Zero Bubble Memory-based Temporal Graph Neural Network Training via Pipeline Optimization · Proc. VLDB Endow. 2025
Distributed systems › fault tolerance
failure recovery
0.312026
ResiHP: Taming LLM Training Failures with Dynamic Hybrid Parallelism · HPDC 2026
High-performance computing
large-scale training
0.312026
ResiHP: Taming LLM Training Failures with Dynamic Hybrid Parallelism · HPDC 2026
Parallel and multicore computing › parallel computing › parallel machine learning
pipelined training
0.312025
PipeTGL: (Near) Zero Bubble Memory-based Temporal Graph Neural Network Training via Pipeline Optimization · Proc. VLDB Endow. 2025

Methods — techniques the papers use, named apart from their topics

runtime analysis DAG · 1.7pipeline parallelism · 1.7communication optimization · 1.7fail-slow detection · 1.0
YearPublicationVenuePosition
2026 ResiHP: Taming LLM Training Failures with Dynamic Hybrid Parallelism
abstract
Hybrid parallelism underpins large-scale LLM training across tens of thousands of GPUs. At such scale, hardware failures on individual devices lead to performance skew across devices, diminishing overall training efficiency. Existing resilient systems overlook sequence length variability in datasets and device performance skew under hybrid parallelism. As a result, (1) iteration time fluctuations induced by sequence length variability can trigger spurious fail-slow detections, and (2) failures are mitigated through individual adaptations in hybrid parallelism, leading to unnecessary detection overhead and inefficient resilient training.
Tenghui Ma, Jihu Guo, Wei Gao 0064, Sitian Lu, Zhisheng Ye 0002, Hanjing Wang, Dahua Lin
HPDC4
2025 PipeTGL: (Near) Zero Bubble Memory-based Temporal Graph Neural Network Training via Pipeline Optimization
abstract
Memory-based Temporal Graph Neural Networks (M-TGNNs) demonstrate superior performance in dynamic graph learning tasks. Their success attributes to a memory module, which captures historical information for each node and implicitly creates a memory dependency constraint among chronologically ordered minibatches. This unique characteristic of M-TGNN introduces new challenges for parallel training that have not been encountered before. Existing parallelism strategies for M-TGNN either sacrifice memory accuracy (minibatch parallelism and epoch parallelism) or compromise space efficiency (memory parallelism) to optimize runtime. This paper proposes a pipeline parallel approach for multi-GPU M-TGNN training that effectively addresses both inter-minibatch memory dependencies and intra-minibatch task dependencies, based on a runtime analysis DAG for M-TGNNs. We further optimize pipeline efficiency by incorporating improved scheduling, finer-grained operation reorganization, and targeted communication optimizations tailored to the specific training properties of M-TGNN. These enhancements significantly reduce GPU waiting and idle time caused by memory dependencies and frequent communication and result in zero pipeline bubbles for common training configurations. Extensive evaluations demonstrate that PipeTGL achieves a speedup of 1.27x to 4.74x over other baselines while also improving the accuracy of M-TGNN training across multiple GPUs.
Jun Liu 0002, Bingqian Du, Ziyue Luo, Sitian Lu, Qiankun Zhang 0001, Hai Jin 0001
Proc. VLDB Endow.4