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Altti Heikkinen

dblp:413/6472 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2025
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 50% Electronic design automation · 50%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
analog and mixed-signal circuits
0.912025
Fully Programmatic Automated Design Procedure of Comparators for Analog-to-Digital Converters · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025
Electronic design automation
analog circuit design automation
0.912025
Fully Programmatic Automated Design Procedure of Comparators for Analog-to-Digital Converters · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025

Methods — techniques the papers use, named apart from their topics

system-level simulation · 0.9parasitic-aware optimization · 0.9
YearPublicationVenuePosition
2025 Fully Programmatic Automated Design Procedure of Comparators for Analog-to-Digital Converters
abstract
This paper proposes a system-aware, fully programmatic and automated, process agnostic design methodology, which utilizes system-level simulations with the layout parasitics of the circuit under optimization included. The methodology is demonstrated with a design procedure for a comparator from specification to layout implementation in three analog-to-digital converter design examples with different specifications and applications without designer interaction. The procedure is shown to effectively converge towards performance achieved with ideal comparator in post-layout across two different semiconductor processes. While the methodology was demonstrated for design of comparators, the proposed system-aware methodology is generally applicable to any analog circuit, drastically reducing design time while providing a silicon ready circuit implementation purpose designed to the higher level system without human-in-the-loop.
Veeti Lahtinen, Santeri Porrasmaa, Altti Heikkinen, Miikka Tenhunen, Jussi Ryynänen, Marko Kosunen
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3