Demo Data from VLDB 2026 / reviewers in the wild / expert
Zhu-Xun Lee
dblp:415/5035
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2025
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › physical design
legalization |
0.9 | 1 | 2025 | Late Breaking Results: Advanced PCB Placement with Irregular Components for Efficient Collision Detection and Routability Optimization · DAC 2025 |
Electronic design automation › physical design › placement › module placement
PCB placement |
0.9 | 1 | 2025 | Late Breaking Results: Advanced PCB Placement with Irregular Components for Efficient Collision Detection and Routability Optimization · DAC 2025 |
Electronic design automation
physical design |
0.9 | 1 | 2025 | Late Breaking Results: Advanced PCB Placement with Irregular Components for Efficient Collision Detection and Routability Optimization · DAC 2025 |
Methods — techniques the papers use, named apart from their topics
separating axis theorem · 0.9scanline-based legalization · 0.9force-directed placement · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Late Breaking Results: Advanced PCB Placement with Irregular Components for Efficient Collision Detection and Routability OptimizationabstractThis paper introduces an automated placement framework to optimize component positioning on modern printed circuit boards (PCBs), addressing challenges posed by heterogeneous components, irregular geometries, and complex design rules. The framework employs three key techniques to enhance placement quality and efficiency: (1) a global placement approach integrating collision detection via the Separating Axis Theorem to handle exact component contours and board shapes, (2) a multi-stage force-directed method that dynamically adjusts attractive and repulsive forces to meet clearance and routability constraints, and (3) a scanline-based legalization technique to resolve overlaps and enforce spacing requirements. Our methodology effectively adapts to diverse design limitations and accelerates the process while preserving placement quality. Experimental results demonstrate that our placer significantly improves routability over state-of-the-art solutions, demonstrating robust performance on industrial PCB designs with complex and irregular constraints. Chien-Hao Tsou, Zhu-Xun Lee, Yao-Wen Chang |
DAC | 2 |