Prabhdeep Singh Soni

dblp:417/7147 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2025
0009-0008-8084-6132ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 87% Embedded and real-time systems · 13%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Compilers and program optimization
program transformation
0.912025
A TRRIP Down Memory Lane: Temperature-Based Re-Reference Interval Prediction For Instruction Caching · MICRO 2025
Memory systems › cache management
cache replacement
0.912025
A TRRIP Down Memory Lane: Temperature-Based Re-Reference Interval Prediction For Instruction Caching · MICRO 2025
Memory systems › cache › CPU cache
instruction cache
0.912025
A TRRIP Down Memory Lane: Temperature-Based Re-Reference Interval Prediction For Instruction Caching · MICRO 2025
Embedded and real-time systems › embedded processor
mobile processor
0.312025
A TRRIP Down Memory Lane: Temperature-Based Re-Reference Interval Prediction For Instruction Caching · MICRO 2025

Methods — techniques the papers use, named apart from their topics

software-hardware co-design · 1.7re-reference interval prediction · 1.7profile-guided optimization · 1.7
YearPublicationVenuePosition
2025 A TRRIP Down Memory Lane: Temperature-Based Re-Reference Interval Prediction For Instruction Caching
abstract
Modern mobile CPU software pose challenges for conventional instruction cache replacement policies due to their complex runtime behavior causing high reuse distance between executions of the same instruction.Mobile code commonly suffers from large amounts of stalls in the CPU frontend and thus starvation of the rest of the CPU resources.Complexity of these applications and their code footprint are projected to grow at a rate faster than available on-chip memory due to power and area constraints, making conventional hardware-centric methods for managing instruction caches to be inadequate.We present a novel software-hardware co-design approach called TRRIP (Temperature-based Re-Reference Interval Prediction) that enables the compiler to analyze, classify, and transform code based on "temperature" (hot/cold), and to provide the hardware with a summary of code temperature information through a well-defined OS interface based on using code page attributes.TRRIP's lightweight hardware extension employs code temperature attributes to optimize the instruction cache replacement policy resulting in the eviction rate reduction of hot code.TRRIP is designed to be practical and adoptable in real mobile systems that have strict feature requirements on both the software and hardware components.TRRIP can reduce the L2 MPKI for instructions by 26.5% resulting in geomean speedup of 3.9%, on top of RRIP cache replacement running mobile code already optimized using PGO.
Henry Kao, Nikhil Sreekumar, Prabhdeep Singh Soni, Ali Sedaghati, Fang Su, Maziar Goudarzi
MICRO3