VLDB 2026 Research / reviewers in the wild / expert
Daan Vanoverloop
dblp:418/8765
· DBLP profile ↗
1ranked-venue papers
1as first author
1since 2021 · last 2025
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Security and privacy · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
1 paper |
Hardware security and side channels · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware security and side channels › trusted execution environments
Intel SGX |
0.9 | 1 | 2025 | TLBlur: Compiler-Assisted Automated Hardening against Controlled Channels on Off-the-Shelf Intel SGX Platforms · USENIX Security Symposium 2025 |
Hardware security and side channels
side-channel countermeasures |
0.9 | 1 | 2025 | TLBlur: Compiler-Assisted Automated Hardening against Controlled Channels on Off-the-Shelf Intel SGX Platforms · USENIX Security Symposium 2025 |
Hardware security and side channels
trusted execution environments |
0.9 | 1 | 2025 | TLBlur: Compiler-Assisted Automated Hardening against Controlled Channels on Off-the-Shelf Intel SGX Platforms · USENIX Security Symposium 2025 |
Methods — techniques the papers use, named apart from their topics
compiler-assisted hardening · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | TLBlur: Compiler-Assisted Automated Hardening against Controlled Channels on Off-the-Shelf Intel SGX Platforms
Daan Vanoverloop, Andrés Sánchez, Flavio Toffalini, Frank Piessens, Mathias Payer, Jo Van Bulck |
USENIX Security Symposium | 1 |