VLDB 2026 Research / reviewers in the wild / expert
David G. Bradlee
dblp:42/1103
· DBLP profile ↗
3ranked-venue papers
3as first author
0since 2021 · last 1991
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 3 · 3 first-authorSystems, architecture and hardware · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
3 papers |
Compilers and program optimization · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Processor architecture and microarchitecture · 100% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Compilers and program optimization
code generation |
0.0 | 2 | 1991 | The Marion System for Retargetable Instruction Scheduling · PLDI 1991 The Effect on RISC Performance of Register Set Size and Structure Versus Code Generation Strategy · ISCA 1991 |
Compilers and program optimization
instruction scheduling |
0.0 | 2 | 1991 | The Marion System for Retargetable Instruction Scheduling · PLDI 1991 Integrating Register Allocation and Instruction Scheduling for RISCs · ASPLOS 1991 |
Compilers and program optimization
register allocation |
0.0 | 2 | 1991 | The Effect on RISC Performance of Register Set Size and Structure Versus Code Generation Strategy · ISCA 1991 Integrating Register Allocation and Instruction Scheduling for RISCs · ASPLOS 1991 |
Processor architecture and microarchitecture › instruction set architecture
RISC |
0.0 | 2 | 1991 | The Effect on RISC Performance of Register Set Size and Structure Versus Code Generation Strategy · ISCA 1991 Integrating Register Allocation and Instruction Scheduling for RISCs · ASPLOS 1991 |
Compilers and program optimization › compiler back end
machine description |
0.0 | 1 | 1991 | The Marion System for Retargetable Instruction Scheduling · PLDI 1991 |
Processor architecture and microarchitecture
instruction set architecture |
0.0 | 1 | 1991 | Integrating Register Allocation and Instruction Scheduling for RISCs · ASPLOS 1991 |
Methods — techniques the papers use, named apart from their topics
performance measurement · 0.0compiler optimization · 0.0retargeting · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1991 | Integrating Register Allocation and Instruction Scheduling for RISCsabstractarticle Free Access Share on Integrating register allocation and instruction scheduling for RISCs Authors: David G. Bradlee View Profile , Susan J. Eggers View Profile , Robert R. Henry View Profile Authors Info & Claims ACM SIGOPS Operating Systems ReviewVolume 25Issue Special IssueApr. 1991 pp 122–131https://doi.org/10.1145/106974.106986Published:01 April 1991Publication History 101citation1,061DownloadsMetricsTotal Citations101Total Downloads1,061Last 12 Months66Last 6 weeks9 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF David G. Bradlee, Susan J. Eggers |
ASPLOS | 1 |
| 1991 | The Effect on RISC Performance of Register Set Size and Structure Versus Code Generation Strategy
David G. Bradlee, Susan J. Eggers |
ISCA | 1 |
| 1991 | The Marion System for Retargetable Instruction Schedulingabstractarticle Free Access Share on The Marion system for retargetable instruction scheduling Authors: David G. Bradlee Department of Computer Science and Engineering, FR-35, University of Washington, Seattle, Washington Department of Computer Science and Engineering, FR-35, University of Washington, Seattle, WashingtonView Profile , Robert R. Henry Tera Computer, 400 N 34th Street, Seattle, WA and Department of Computer Science and Engineering, FR-35, University of Washington, Seattle, Washington Tera Computer, 400 N 34th Street, Seattle, WA and Department of Computer Science and Engineering, FR-35, University of Washington, Seattle, WashingtonView Profile , Susan J. Eggers Department of Computer Science and Engineering, FR-35, University of Washington, Seattle, Washington Department of Computer Science and Engineering, FR-35, University of Washington, Seattle, WashingtonView Profile Authors Info & Claims ACM SIGPLAN NoticesVolume 26Issue 6June 1991 pp 229–240https://doi.org/10.1145/113446.113465Published:01 May 1991Publication History 36citation502DownloadsMetricsTotal Citations36Total Downloads502Last 12 Months28Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF David G. Bradlee, Susan J. Eggers |
PLDI | 1 |