This paper presents significant improvements to our previous watermarking technique for Intellectual Property Protection (IPP) that enables the protection of IP cores. The technique relies on hosting the bits of a digital signature at the HDL design level using combinational logic included within the original system. Thus, any attack trying to change or remove the digital signature will damage the design. The technique also includes a procedure for secure signature extraction. The new advances refer to increasing the applicability of this watermarking technique to any design and the provision of an automatic tool for signature hosting purposes. The design examples on FPL devices show the effectiveness of this watermarking technique. Synthesis results show that the application of the proposed watermarking strategy results in negligible degradation of system performance and very low area penalties.

In this paper, a procedure for intellectual property protection (IPP) of digital circuits called IPP@HDL is presented. Its aim is to protect the author rights in the development and distribution of reusable modules by means of an electronic signature. The technique relies on hosting the bits of the digital signature within memory structures or combinational logic that are part of the system, at the high level description of the design. Thus, the area of the system is not increased and the signature is difficult to change or to remove without damaging the design. The technique also includes a procedure for secure signature extraction requiring minimal modifications to the system and without interfering its normal operation. The benefits of the presented procedure are illustrated with programmable logic and cell-based application-specific integrated circuit examples with several signature lengths. These design examples show no performance degradation and a negligible area increase, while probabilistic analyses show that the proposed IPP scheme offers high resistance against attacks.

This paper presents a technique for intellectual property protection (IPP) of systems to be implemented over programmable devices. The aim is to protect the author rights of reusable IP cores by means of a digital signature that uniquely identifies both the original design and the design recipient. The technique relies on a procedure that spreads a digital signature in cells of look-up tables of designs at HDL design level, not increasing the area of the system. The technique includes a procedure for signature extraction requiring minimal modifications to the system. So it is possible to detect the ownership rights without interfering the normal operation of the system. The IPP technique has been implemented on FPL devices, not disrupting the functionality neither significantly degrading the performance.

The discrete wavelet transform is routinely used in numerous applications and its efficient implementation in VLSI technology is a subject of continuous research. This paper shows the implementation of reduced complexity and high performance polyphase wavelet filter banks using Galois field arithmetic. The proposed designs are compared to traditional systems using 2's complement (2C) arithmetic with the proposed architectures being about 65% faster than 2C designs and requiring less logic in most study cases.

The need for both speed and increased precision in modern digital signal processing (DSP) applications represents a serious implementation obstacle. The paper explores the arithmetic benefits provided by the residue number system (RNS) for the design of such systems. Specifically, the fusion of the RNS with the popular distributed arithmetic (DA) is considered for the implementation of a discrete wavelet transform (DWT) filter bank. An exhaustive comparison of the advantages of RNS-DA over the traditional two's complement design, 2C-DA, is carried out for field-programmable logic (FPL), and cell-based ASIC technologies. The results show that the reported RNS-DA methodology, compared to a traditional 2C-DA design, enjoys a significant performance advantage that increases with precision.

A new methodology to compute the N-point DCT (Discrete Cosine Transform) in the QRNS (Quadratic Residue Number System) is presented, with a significant improvement in complexity and speed compared to the corresponding binary version. This reduction in the total number of arithmetic adders and multipliers is up to 21% and 26% for an 8-point and a 16-point DCT, respectively. In addition, large and slow binary adders and multipliers with a long carry propagation delay are replaced by high-speed small word-length modular adders and LUT (Look-Up Table) multipliers. When a Field Programmable Logic (FPL) implementation using Altera FLEX10KE devices of the proposed architecture for the 8-point DCT is considered, throughput is three times better than that obtained with the corresponding fixed point 2's complement binary implementation.

Previous scaling schemes have used iterative algorithms, which lead to computation time and memory requirements that increase with the number of moduli. This paper presents a two look-up cycle scaling scheme which allows a diminution of the required memory when nonlarge sets of moduli are considered. This scheme can be combined with previous algorithms for larger sets of moduli.

The use of generalized Hopfield neural networks in designing the checking circuitry of a concurrent testable circuit is discussed. The aliasing probability, a measure for evaluating the performance of the checking circuitry, is provided. It is shown how, by using spectral techniques based on the Reed-Muller transform, the aliasing probability can be expressed as a function of the Reed-Muller coefficients. Therefore, obtaining the checking circuitry means selecting a set of Reed-Muller spectral coefficients, with fewer elements than a given bound, that minimizes the aliasing probability. To apply the neural networks to design the checking circuitry for concurrent testing, the aliasing probability has been used as an energy function, and the Hopfield neural network has been modified to have an associated energy function with any type of polynomial dependence on the processor states.>

Reed-Muller coefficients are used to generate a test-pattern selection procedure for detecting single stuck-at faults. This procedure is based on the heuristics deduced from the way in which the spectral coefficients are affected by such faults. The changes that the spectral coefficients undergo are also compared with the fault models used most frequently to model defects in combinational circuits. The proposed pattern-generating procedure does not need a simulation of the circuit for each of the possible stuck-at faults, and its complexity is proportional to the number of gates in the circuit. The proportionality constant increases exponentially as the number of inputs in the circuit increases. To evaluate the performance of the proposed method, its application to some benchmark circuits, including the ALU 74181, is presented.>

Several problems in switching theory such as automatic test pattern generation, can be exactly and elegantly investigated by using switching equations. An efficient tabular method is presented to solve these switching equations. The solutions of a given equation are compacted into a table, and a Boolean algebra is defined for these tables. The proposed procedure is based on the use of this Boolean algebra. The compactness and simplicity of the method are outstanding, and it is straightforward to implement for computer processing. The complexity of the procedure is computed, and some experimental results for a set of benchmark equations are provided in order to point out the effectiveness of this method.>