Linear Feedback Shift Registers (LFSRs) have been extensively used for compressed manufacturing test. They have been recently employed as a foundation for porting constrained-random stimuli from a pre-silicon verification environment to in-system validation. This work advances this concept by improving both the hardware efficiency and the duration of in-system validation experiments.

When generating the verification stimuli in a pre-silicon environment, the primary objectives are to reduce the simulation time and the pattern count for achieving the target coverage goals. In a hardware environment, because an increase in the number of stimuli is inherently compensated by the advantage of real-time execution, the objective augments to considering hardware complexity when designing in-system stimuli generators that must operate according to user-programmable constraints. In this paper we introduce a structured methodology for porting in-system the constrained-random stimuli generation aspect from a pre-silicon verification environment.

While a large body of work on output unknown (X) tolerance exists, to the best of the authors' knowledge, no study is provided in the literature which explores the trade-off between X density and compression of circuit stimuli without reducing fault coverage. To this end, we introduce an architectural and algorithmic framework through which we explore this trade-off, the findings of which we discuss in the experimental results section.

As interest mounts in using hardware accelerators to speed up numerical scientific calculations, automation tool support is required to aid designers in mapping applications to custom hardware. One key step in designing this custom hardware is bit-width allocation where the known-art faces challenges when dealing with applications from the scientific computing domain, thus motivating the use of computational methods based on Satisfiability-Modulo Theory. Many real-life applications are, however, specified in terms of vectors and matrices which are of sufficient size to make expansion into scalar equations infeasible. The proposed vector-magnitude method and its extension via block vectors enable computational methods to be leveraged in tackling calculations of practically relevant complexity. Application to case studies confirms that through a more compact computational instance, search efficiency is improved leading to tighter bounds and thus smaller bit-widths.

As scientific computing becomes more widespread in environments where form-factor considerations necessitate hardware acceleration, the problem of selecting numerical data representations (bit-width allocation), key to accelerator design, is faced with shortcomings in the existing techniques. To address this problem for scientific computing dataflows, we propose a methodology for determining custom hybrid fixed/floating-point data representations for iterative computations.

This paper details our experience of developing an MPEG-2 audio/video decoder which operates at main level/main profile, 720 × 480 4:2:0 at 29.97 frames per second, with audio at 16 bits, 48 000 samples per second. The design has been developed with a focus on energy-efficiency.

In multi-core designs, distributed embedded logic analyzers with multiple trigger units and trace buffers with real-time offload capability through high-speed trace ports can be placed on-chip. This brings new challenges on how to connect the debug units together in such way that the limited storage space in the trace buffers can be used efficiently. This problem is further aggravated when shadow registers are used to capture data for some signals in the design. In this paper, we propose a new architecture that can dynamically allocate the trace buffers at runtime based on the needs for debug data acquisition coming from multiple data sources and user-programmable priorities. Experimental results show that using the proposed architecture, real-time observability can be improved using only a small amount of on-chip logic hardware, while avoiding excessive storage on-chip.

The ubiquity of embedded systems of increasing complexity in domains like scientific computing requires computation on models whose complexity has grown beyond what is economical to manage purely in software to requiring hardware acceleration - a key part of which is selecting numerical data representations (bit-width allocation). To address the shortcomings of existing techniques when applied to scientific computing dataflows, we propose a methodology for determining custom hybrid fixed/floating-point data representations for iterative scientific computing applications.

This paper investigates the application of computational methods via Satisfiability Modulo Theory (SMT) to the bit-width allocation problem for finite precision implementation of numerical calculations, specifically in the context of scientific computing where division frequently occurs. In contrast to the large body of work targeted at the precision aspect of the problem, this paper addresses the range problem where employing SMT leads to more accurate bounds estimation than those provided by other analytical methods, in turn yielding smaller bit-widths, and hence a reduction in hardware cost and/or increased parallelism, while maintaining robustness as is necessary for scientific applications.

In this paper we observe that the necessary amount of compressed test data transferred from the tester to the embedded cores in a system-on-a-chip (SOC) varies significantly during the testing process. This motivates a novel approach to compressed system-on-a-chip testing based on time-multiplexing the tester channels. It is shown how the introduction of a few control channels will enable the sharing of data channels, on which compressed seeds are passed to every embedded core. Through the use of modular and scalable hardware for on-chip test control and test data decompression, we define a new algorithmic framework for test data compression that is applicable to system-on-a-chip devices comprising intellectual property-protected blocks.

This paper explores the use of SAT-Modulo Theory in determination of bit-widths for finite precision implementation of numerical calculations, specifically in the context of scientific computing where division frequently occurs. Employing SAT-Modulo Theory leads to more accurate bounds estimation than those provided by other analytical methods, in turn yielding smaller bit-widths.

Automated bit-width allocation is a key step required for the design of hardware accelerators. The use of computational methods based on SAT-Modulo Theory to the problem of finite-precision bit-width allocation has recently been shown to overcome challenges faced by the known-art, particularly in the scientific computing domain. However, many such real-life applications are specified in terms of vectors and matrices and they are rendered infeasible by expansion into scalar equations. This paper proposes a framework to include operations from vector calculus and thus it enables tackling applications of practically relevant complexity.

In this work, a new hardware-based parallel implementation of the iterative conjugate gradient (CG) algorithm for solving such systems of equations is proposed. Fixed point computations are employed to optimize hardware resource usage and to increase parallelism. The proposed implementation adaptively adjusts to variations in the dynamic range of data operands in order to enhance computation accuracy and avoid divergence due to overflow and quantization errors.

Post-silicon validation is used to identify design errors in silicon. Its main limitation is real-time observability of the circuit's internal nodes. In this paper, we introduce a novel design-for-debug architecture which automatically allocates distributed trace buffers to handle debug data acquisition requests from multiple sources located in different cores. Using resource-efficient and intelligent control placed on-chip, we show how real-time observability can be improved, thus helping bridge the gap between pre-silicon verification and post-silicon validation for SOC designs.

While manufacturing test helps to isolate faulty devices from the good ones, diagnosis is enabling a faster transition from the yield learning to the volume production phase of a new process technology. Given the escalating design complexity, new methods such as embedded deterministic test have been proposed in recent years to deal with the cost of manufacturing test. This paper discusses diagnosis of logic blocks by leveraging the existing embedded deterministic test hardware. The proposed method is based on new techniques for on-chip decompression and comparison of incompletely specified test patterns and test responses. Using experimental data, the tradeoffs between the number of tester channels, on-chip area, and scan time are discussed.

In this paper we first observe that the required amount of compressed test data transferred from the tester to the embedded cores in a system-on-a-chip (SOC) varies significantly during the testing process. This motivates a new approach to test data compression, mainly applicable to core-based SOCs, based on time-multiplexing the tester channels through which the on-chip decompressors will receive compressed test data only when necessary. The distinguishing advantage of this approach is that it is suitable for concurrent testing of multiple cores in an SOC and not only will the volume of test data be reduced but also the tester channel utilization will be increased.

This paper introduces a new method for deterministic diagnosis of logic cores. The proposed method is based on on-chip decompression and comparison of incompletely specified test patterns and test responses. Using experimental data, the trade-offs between the number of tester channels, on-chip area and scan time are discussed.