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Roberto Guizzetti

dblp:42/2048 · DBLP profile ↗
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17ranked-venue papers
0as first author
3since 2021 · last 2024
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 6Systems, architecture and hardware · 2 · 1 since 2021Artificial intelligence and machine learning · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › formal verification
equivalence checking
0.112008
Leveraging sequential equivalence checking to enable system-level to RTL flows · DAC 2008
Electronic design automation
hardware verification and test
0.112008
Leveraging sequential equivalence checking to enable system-level to RTL flows · DAC 2008
Electronic design automation › hardware verification and test › formal verification
sequential equivalence checking
0.112008
Leveraging sequential equivalence checking to enable system-level to RTL flows · DAC 2008
Electronic design automation
high-level synthesis
0.012008
Leveraging sequential equivalence checking to enable system-level to RTL flows · DAC 2008

Methods — techniques the papers use, named apart from their topics

sequential equivalence checking · 0.1
YearPublicationVenuePosition
2024 GemIMC: A Configurable HW Architecture for Technology Agnostic IMC Based NN Inference
abstract
This paper presents GemIMC, a High Level Synthesis (HLS) based configurable digital unit architecture for accelerating Neural Networks (NN) at the edge using In Memory Computing (IMC). The proposed architecture is capable of supporting any type of memory technology, be it CMOS or resitive, with digital or analog storage capabilities. GemIMC aims to facilitate design space exploration among different IMC-related parameters and provide a top architecture for prototyping. By taking as input the IMC-tile parameters such as storage type (analog/digital), size, latency, power and process variability, GemIMC provides a an estimation of the full system's latency, area, and power consumption, taking into account the full digital control. The Tensorfiow-to-GemIMC environment flow allows for direct evaluation of the ineference accuracy for any type of NN, considering the variability associated with analog computation (when needed). The proposed work provides a flexible and efficient solution for IMC-based NN inference on the edge, along with a methodology for writing the IMC tile model to ensure compatibility with the top architecture.
Emilien Taly, Roberto Guizzetti, Pascal Urard, Elena I. Vatajelu
VLSI-SoC2
2023 Quantization Modes for Neural Network Inference: ASIC Implementation Trade-offs
abstract
As deep neural networks migrate close to the sensors, accuracy cannot be the single target anymore: inference tasks must also be highly energy efficient. For embedded devices, the power budget for one inference is typically in the range of a few tens of µW to single-digit mW. We have three levers of action for that: computational workload, number of values to memorize-be they network parameters or intermediate activation results-, and implementation strategy. Given the fact that Application Specific Integrated Circuits are two orders of magnitude more power-efficient than processors for a given technology node, the latter issue is solved using ad-hoc hardware implementations. For the two first former issues, we detail and compare in this work different existing quantization approaches, since reducing the number of bits of the weights and activations reduces computation complexity and storage needs. In addition, we also propose two new modes specifically aiming at low silicon footprint and power optimized hardware implementations that still provide an accuracy in par with existing works. We report the area/power and accuracy trade-offs all theses quantization modes provide when targeting low to ultra-low power devices. The evaluation is done using STMicroelectronics 40nm technology. It shows that the best results vary depending on the dataset and network architecture, which calls for application and quantization aware network architecture search.
Nathan Bain, Roberto Guizzetti, Emilien Taly, Ali Oudrhiri, Bruno Paille, Pascal Urard, Frédéric Pétrot
IJCNN2
2023 Performance Modeling and Estimation of a Configurable Output Stationary Neural Network Accelerator
abstract
Neural network accelerators are designed to process Neural Networks (NN) optimizing three Key Performance Indicators (KPIs): latency, power, and chip area. This work is based on the study of Gemini, an industrial prototype near memory computing inference accelerator designed using a high-level synthesis technique. Gemini is an output stationary configurable accelerator that achieves its performance based on two structural parameters. The measurement of the KPIs requires simulations that are time-consuming and resource-intensive. This paper presents a high-level practical estimator that can instantly predict the KPIs depending on the NN and the Gemini configuration. The latency is accurately derived using an analytical model based on the architecture, the operators scheduling and the NN characteristics. The power and the chip area are computed analytically and the models are calibrated using simulations. Finally, we show how to use the estimator to derive Pareto optima for choosing the best Gemini configurations for a VGG-like NN.
Ali Oudrhiri, Emilien Taly, Nathan Bain, Alix Munier Kordon, Roberto Guizzetti, Pascal Urard
SBAC-PAD5
2018 BLE Parameter Optimization for IoT Applications
abstract
Bluetooth Low Energy (BLE) has been designed as a power efficient protocol for small portable and autonomous devices, showing its efficiency for connecting these devices with smartphones to periodically and frequently exchange data, like heart rate or notifications. Additionally, BLE is present in almost every smartphone, turning it into perfect ubiquitous remote control for smart homes, buildings or cities. Nevertheless, there is still room to improve BLE performance for typical IoT use cases where battery lifetime should reach several years. In this paper we propose an extension to a model for evaluating BLE performance, latency and energy consumption, in order to provide realistic results based on various scenario conditions. In addition, we propose a parameter optimization of the BLE Neighbor Discovery process, in order to obtain the best performance possible depending on the constraints of specific use cases. Our results on two typical IoT test-cases show that advertiser battery lifetime can be increased up to ~89x (9.55 days to 2.32 years) for a first case, and ~281x (9.55 months to 7.36 years) for a second case.
Andreina Liendo, Dominique Morche, Roberto Guizzetti, Franck Rousseau
ICC3
2018 Efficient Bluetooth Low Energy Operation for Low Duty Cycle Applications
abstract
Bluetooth Low Energy (BLE) has shown higher energy efficiency and robustness than other well known Wireless Sensor Network (WSN) protocols, making it a strong candidate for implementation in IoT scenarios. In addition, BLE is in almost every smartphone, turning it into perfect ubiquitous remote controls for smart homes, buildings or cities. In this paper we propose new operating modes for BLE to provide a much wider applicability range covering asynchronous, aperiodic and very low frequency scenarios while extending lifetime, without modification of the existing BLE specification. In order to estimate battery lifetime, we propose a coin cell battery model. We show how to efficiently adapt the protocol for different IoT scenarios based on their requirements, thus extending battery lifetime as much as possible while guaranteeing acceptable latency. Our results on two typical test-cases show that by using an optimized configuration and appropriate operating mode based on scenario requirements, lifetime can be increased up to ≈2× (4.1 to 7.3 years) for a BLE master in a first case, and ≈ 58× (3.05 months to 14.82 years) for a BLE slave in a second case. This shows BLE compatibility with a vast amount of IoT-related use cases.
Andreina Liendo, Dominique Morche, Roberto Guizzetti, Franck Rousseau
ICC3
2018 DataJoin: An Energy-Efficient Joining Scheme for 802.15.4e TSCH Networks
abstract
This paper considers the problem of a node joining an existing 802.15.4e TSCH network. We propose DataJoin, an energy-efficient scheme based on two ideas: i) it schedules the transmission of enhanced beacon frames in a smart way by taking advantage of the information on the common TSCH schedule and ii) it piggybacks the next beacon transmission times onto some acknowledgment frames to allow a joining node to overhear this information. We compare DataJoin with the Baseline scheme that corresponds to the state-of-the-art protocol for joining TSCH networks. Simulation comparisons show lower energy consumption by the joining node under DataJoin along with similar joining delays and average network energy consumption for both schemes.
Elodie Morin, Mickael Maman, Roberto Guizzetti, Andrzej Duda
WiMob3
2017 Singer cyclic difference sets for an energy-efficient joining scheme
abstract
This paper considers the problem of joining a network of constrained IoT devices. We propose to take advantage of Singer Cyclic Difference Sets (S-CDS) for a joining scheme that results in low duty cycles and apply the proposed scheme to the joining problem in 802.15.4e TSCH networks. S-CDS distributes the active periods of nodes over time so that a joining node does not suffer from long scanning periods in contrast to other schemes. We compare S-CDS through simulation with other state-of-the-art schemes adapted to TSCH networks. The comparisons show that S-CDS achieves a better trade-off between energy consumption and joining delay than the best joining schemes while being particularly suitable for devices with strong energy constraints such as energy harvesting nodes.
Elodie Morin, Mickael Maman, Roberto Guizzetti, Andrzej Duda
WiMob3
2016 Improving robustness of beacon-enabled IEEE 802.15.4 with Round-Robin channel diversity
abstract
Reliable wireless communication even in adverse conditions is the key for building the energy efficient and dependable Internet of Things. In this paper, we explore the benefits of channel diversity for enabling efficient wireless communication: we propose MRR (Multi-channel Round-Robin), a backward-compatible evolution of beacon-enabled IEEE 802.15.4 in which energy constrained nodes take advantage of additional active periods operating on different channels in a round-robin way. Each active period starts with a beacon sent on a cyclically changing channel, which then allows an associated device to transmit data on the channel used for the beacon. MRR schedules the additional active periods at carefully selected instants to avoid direct beacon collisions. To motivate our work, we first experimentally corroborate previous findings that channel diversity is an effective way of mitigating variable or poor transmission conditions. Then, we observe that channel diversity improves the quality of transmission even better than expected - it appears that wireless sensor nodes have a radiation pattern that changes significantly from one frequency channel to another, which often results in a considerably improved gain when using the right communication channel. The evaluation of the MRR scheme through measurements on a real indoor multihop testbed shows that the proposed scheme results in significantly improved Packet Reception Ratio even without resorting to e.g. channel blacklisting. These results confirm the benefits of multichannel operation and exhibit a fully functional solution that does not add a large overhead compared to using a single channel.
Liviu-Octavian Varga, Martin Heusse, Roberto Guizzetti, Andrzej Duda
PIMRC3
2016 Energy consumption and performance of IEEE 802.15.4e TSCH and DSME
abstract
The recent IEEE 802.15.4e standard has introduced two interesting modes of operation: Time Slotted Channel Hopping (TSCH) and Deterministic and Synchronous Multi-channel Extension (DSME). Both provide a mix of time and frequency division to improve the performance of the previously available synchronized MAC mode (beacon-enabled 802.15.4). In this paper, we compare the performance of DSME and TSCH with respect to the energy consumption, throughput, and delay through an analysis of their respective ways of operation. We use an energy consumption model coming from our previous experience on the design of recent energy harvesting motes for the GreenNet platform. Our results show that DSME performs slightly better in terms of the energy consumption spent in data transfers. Both protocols exhibit similar delays for a given duty cycle, nevertheless, TSCH obtains shorter delay and higher throughput for low duty cycles. For higher duty cycles, TSCH results in lower throughput - for applications that send little data, the fixed slot configuration of TSCH results in wasted bandwidth. DSME can allocate shorter slots, which is beneficial for applications that transmit short packets.
Iacob Juc, Olivier Alphand, Roberto Guizzetti, Michel Favre, Andrzej Duda
WCNC3
2015 DTLS performance in duty-cycled networks
abstract
The Datagram Transport Layer Security (DTLS) protocol is the IETF standard for securing the Internet of Things. The Constrained Application Protocol, ZigBee IP, and Lightweight Machine-to-Machine (LWM2M) mandate its use for securing application traffic. There has been much debate in both the standardization and research communities on the applicability of DTLS to constrained environments. The main concerns are the communication overhead and latency of the DTLS handshake, and the memory footprint of a DTLS implementation. This paper provides a thorough performance evaluation of DTLS in different duty-cycled networks through real-world experimentation, emulation and analysis. In particular, we measure the duration of the DTLS handshake when using three duty cycling link-layer protocols: preamble-sampling, the IEEE 802.15.4 beacon-enabled mode and the IEEE 802.15.4e Time Slotted Channel Hopping mode. The reported results demonstrate surprisingly poor performance of DTLS in radio duty-cycled networks. Because a DTLS client and a server exchange more than 10 signaling packets, the DTLS handshake takes between a handful of seconds and several tens of seconds, with similar results for different duty cycling protocols. Moreover, because of their limited memory, typical constrained nodes can only maintain 3–5 simultaneous DTLS sessions, which highlights the need for using DTLS parsimoniously.
Malisa Vucinic, Bernard Tourancheau, Thomas Watteyne, Franck Rousseau, Andrzej Duda, Roberto Guizzetti, Laurent Damon
PIMRC6
2015 Sustainable Traffic Aware Duty-Cycle Adaptation in Harvested Multi-Hop Wireless Sensor Networks
abstract
Sustainable power management techniques in energy harvesting wireless sensors currently adapt the consumption of sensors to their harvesting rate within the limits of their battery residual energy, but regardless of the traffic profile. To provide a fairer distribution of the energy according to application needs, we propose a new sustainable traffic aware duty-cycle adaptation scheme (STADA) that takes into account the traffic load in addition to previous factors. We evaluate our protocol in the specific context of multi-hop IEEE 802.15.4 beacon-enabled wireless sensor networks powered by solar energy. Simulations show that our solution outperforms traffic-unaware adaptation schemes while minimizing the variance of the quality of service provided to applications.
Gabriele Romaniello, Olivier Alphand, Roberto Guizzetti, Andrzej Duda
VTC Spring3
2015 OSCAR: Object security architecture for the Internet of Things
Malisa Vucinic, Bernard Tourancheau, Franck Rousseau, Andrzej Duda, Laurent Damon, Roberto Guizzetti
Ad Hoc Networks6
2015 GreenNet: An Energy-Harvesting IP-Enabled Wireless Sensor Network
abstract
This paper presents GreenNet, an energy efficient and fully operational protocol stack for IP-enabled wireless sensor networks based on the IEEE 802.15.4 beacon-enabled mode. The stack runs on a hardware platform with photovoltaic cell energy harvesting developed by STMicroelectronics (STM) that can operate autonomously for long periods of time. GreenNet integrates several standard mechanisms and enhances existing protocols, which results in an operational platform with the performance beyond the current state of the art. In particular, it includes the IEEE 802.15.4 beacon-enabled medium access control (MAC) integrated with lightweight IP routing for achieving very low duty cycles. It offers an advanced discovery scheme that accelerates the process of joining the network and proposes an adaptation scheme for adjusting the duty cycle of harvested nodes to the available energy for increased performance. Finally, it supports security at two levels: a basic standard secure operation at the link layer and advanced scalable data payload security. This paper describes all techniques and mechanisms for saving energy and operating at very low duty cycles. It also provides an evaluation of the performance and energy consumption of GreenNet.
Liviu-Octavian Varga, Gabriele Romaniello, Malisa Vucinic, Michel Favre, Andrei Banciu, Roberto Guizzetti, Christophe Planat, Pascal Urard, Martin Heusse, Franck Rousseau, Olivier Alphand, Etienne Dublé, Andrzej Duda
IEEE Internet Things J.6
2014 Expected delay for topology construction and reconfiguration in harvested 802.15.4 networks
abstract
Multi-hop harvested wireless sensor networks (HWSN) face two challenges. First, each node must control its energy consumption through duty cycle adaptation to spend less energy than nodes obtain from the environment. Second, nodes must efficiently adapt topology so that packets use the most efficient paths towards the sink. In this paper, we address the challenges in the specific context of beacon-enabled IEEE 802.15.4 networks that harvest energy from the light. We analyze and discuss the integration of duty cycle adaptation and topology reconfiguration algorithms in this kind of networks. We propose a novel scheme to identify the best route using the Expected Delay metric (ED). ED synthesizes several network path factors in a single monotonic value that may be used to choose the parent node in topology construction. We have evaluated the performance of the proposed scheme and compared it with the DEHAR routing protocol. Our simulations show the better performance of the proposed scheme.
Gabriele Romaniello, Olivier Alphand, Andrzej Duda, Roberto Guizzetti
WiMob4
2014 OSCAR: Object security architecture for the Internet of Things
abstract
Billions of smart, but constrained objects wirelessly connected to the global network require novel paradigms in network design. New protocol standards, tailored to constrained devices, have been designed taking into account requirements such as asynchronous application traffic, need for caching, and group communication. The existing connection-oriented security architecture is not able to keep up-first, in terms of the supported features, but also in terms of the scale and resulting latency on small constrained devices. In this paper, we propose an architecture that leverages the security concepts both from content-centric and traditional connection-oriented approaches. We rely on secure channels established by means of (D)TLS for key exchange, but we get rid of the notion of the “state” among communicating entities. We provide a mechanism to protect from replay attacks by coupling our scheme with the CoAP application protocol. Our object-based security architecture (OSCAR) intrinsically supports caching and multicast, and does not affect the radio duty-cycling operation of constrained objects. We evaluate OSCAR in two cases: 802.15.4 Low Power and Lossy Networks (LLN) and Machine-to-Machine (M2M) communication for two different hardware platforms and MAC layers on a real testbed and using the Cooja emulator. We show significant energy savings at constrained servers and reasonable delays. We also discuss the applicability of OSCAR to Smart City deployments.
Malisa Vucinic, Bernard Tourancheau, Franck Rousseau, Andrzej Duda, Laurent Damon, Roberto Guizzetti
WoWMoM6
2013 Fast and energy-efficient topology construction in multi-hop multi-channel 802.15.4 networks
abstract
In multi-hop IEEE 802.15.4 networks with nodes operating in the beacon-enabled mode, the time and energy spent in the cluster-tree construction may be long and highly variable especially if there are no a priori restrictions on duty-cycle durations or on the channels used in the network. In this paper, we propose a Multi-Channel Beacon Train (MCBT) protocol in which coordinator nodes send trains of beacons on all channels at random instants during the inactive part of a superframe, so that nodes entering the network can quickly acquire the network parameters or routing metrics and join the network. The scheme drastically shortens the delay for topology construction and lowers the consumed energy.
Gabriele Romaniello, Emmanouil Potetsianakis, Olivier Alphand, Roberto Guizzetti, Andrzej Duda
WiMob4
2008 Leveraging sequential equivalence checking to enable system-level to RTL flows
abstract
It has long been the practice to create models in C or C++ for architectural studies, software prototyping and RTL verification in the design of Systems-on-Chip (SoC). It is often the case that by the end of a design project, multiple C models exist for different uses. Since a lot of time is invested in ensuring the functional correctness of these models via their use in system-level simulations, they often become "golden" functional reference models. Design teams are moving towards leveraging these system-level models to reduce the time needed for design and verification of RTL. On the design side, the use of high-level synthesis tools to synthesize RTL from C/C++ models is gaining ground for certain classes of blocks within a design. On the verification front, temporal differences at interfaces and in internal states between system-level models and RTL prevent the use of combinational equivalence checkers. This paper focuses on the use of sequential equivalence checking to verify functional equivalence between system-level models and RTL and describes the challenges and vale of using it in system-level to RTL flows.
Pascal Urard, Asma Maalej, Roberto Guizzetti, Nitin Chawla
DAC3