This paper presents a resource optimized hardware solution to perform the H.264 8x8 inverse transform. Row/column decomposition is used, arithmetic units are re-used and the transpose memory is replaced by a shift register. The architecture is able to perform 8x8 integer transform calculation in 144 cycles with as few as 431 LUTs on a Xilinx virtex 6 FPGA for 16-bit resolution. To enable the module to process all inverse transforms in H.264, the number of LUTs is increased to 681. When used to calculate all transforms for H.264 videos, the design supports resolutions up to 1280x720@30fps when running at 84 MHz.

RF test signals are a requirement for the implementation of effective BIST techniques in transceivers. In this work a method to encode a binary signal with the desired RF frequency is presented. The approach employs high-pass sigma delta modulators, in contrast to conventional low- pass or band-pass approaches, allowing signal generation close to the Nyquist limit of FS/2 (FS=sampling frequency). As a digital signal is used, only a 1-bit DAC is needed, reducing test costs. Practical results using a 3Gbps transceiver illustrate the performance achievable by the method.

One of the main problems when developing analog filters in VLSI is to achieve high accuracy regarding the cutoff frequency. This is mainly due to the difficulty in obtaining accurate time constants. Testing of such filters is also challenging, in the sense that special equipment is required. Small deviations in the resistor or capacitor values may lead to a very high mismatch between the expected and the achieved cutoff frequency. Although switched-capacitor or active-transistor techniques may produce good results, the cost to use such approaches becomes another limiting factor, and only increases the tester needs. In this work, we present the development of an analog FIR filter, which does not use passive components to tune the cutoff frequency or the quality factor. Instead, the filter coefficients and the input signal are represented in a bit stream fashion, and are digitally processed, thus avoiding the use of expensive analog-to- digital converters. The impact of this filter architecture on test cost and possible design-for-test techniques are discussed in this paper.

This paper discusses low cost RF signal generation for BIST, using only digital circuits. One major problem is the range of frequencies that can be achieved by any digital signal generator, since the Nyquist limit is the clock frequency divided by 2 (FS/2). The proposed method uses the images of the signal in order to reach frequencies beyond FS/2. Different digital signal generation techniques for RF and their limitations are addressed as well as their impact in the framework of analog RF BIST. Experimental results and comparisons are provided using a gigabit transceiver

In this work a method to improve the loopback test used in RF analog circuits is described. The approach is targeted to the SoC environment, being able to reuse system resources in order to minimize the test overhead. An RF sampler is used to observe spectral characteristics of the RF signal path during loopback operation. While able to improve the observability of the signal path, the method also allows faster diagnosis than conventional loopback tests, as the number of transmitted symbols can be greatly reduced. Practical results for a prototyped RF link at 860MHz are presented in order to demonstrate the relevance of the method

A technique for noise figure evaluation, suitable for BIST implementation, is described. It is based on a low cost single-bit digitizer, which allows the simultaneous evaluation of the noise figure in several test points of the analog circuit. The method is also able to benefit from SoC resources, like memory and processing power. The theoretical background and experimental results are presented in order to demonstrate the feasibility of the approach.

A low cost method for testing analogue RF signal paths suitable for BIST implementation in a SoC environment is described. The method is based on the use of a simple and low-cost one-bit digitizer that enables the reuse of processor and memory resources available in the SoC, while incurring little analogue area overhead. The proposed method also allows a constant load to be observed by the circuit, since no switches or muxes are needed for digitizing specific test points. Mathematical background and experimental results are presented in order to validate the test approach.

This work presents some results regarding the development of a BIST technique capable of noise figure evaluation. Noise figure is an important parameter in the specification and design of low noise systems, such as communications systems and biomedical instrumentation. A review of published techniques for noise figure evaluation is provided. A new technique aimed to estimate noise figure in a SoC environment is then proposed. The technique is based on the use of a simple and low cost noise generator. Simulation results are provided in order to make an initial evaluation of the feasibility of the proposed approach.

In this work a BIST method for linear analog circuits with very low cost and the smallest possible analog overhead area is presented. The method is suitable to be implemented in the SoC environment, as it allows the reuse of resources already available in the system, and it is essentialy digital. Theoretical background is provided, and experimental results demonstrate the advantages and limits of the proposed approach.

In this work, a low cost method to implement an analog BIST scheme for the system on chip environment is presented. The method is based on spectral analysis and it is entirely digital. A simple and low cost 1-bit digitizer is used to capture analog information without the need for an AD converter or oversampling techniques. It also allows partitioning of the analog circuit for test thanks to the low analog area overhead of the digitizer. The mathematical framework and a test example are presented, with practical results illustrating limitations and advantages of the proposed technique.

This paper presents the development of some front-end analog circuits for mixed signals systems. The paper proposes the use of externally linear internally nonlinear analog circuits. Using this approach, analog area is greatly reduced and circuits can be built on top of completely digital technologies. Experimental results in the analog and digital domain support the proposed approach to mixed circuits design.

This papers describes a new, fast and economical methodology to test linear analog circuits based on adaptive algorithms. To the authors knowledge, this is the first time such technique is used to test analog circuits, allowing complete fault coverage. The paper presents experimental results showing easy detection of soft, large-deviation and hard faults, with low cost instrumentation. Components variations from 5 % to 1 % have been detected, as the comparison parameter (output error power) varied from 300 % to 20%. 1 Introduction and