There is a need for an efficient design-for-testability to satisfy both testability and security of digital circuits. In our previous work, we reported a secure and testable scan design approach by using extended shift registers that are functionally equivalent but not structurally equivalent to shift registers, and showed a security level by clarifying the cardinality of those classes of shift register equivalents (SR equivalents). However, SR equivalents are not always secure for scan-based side-channel attacks. In this paper, we consider a scan-based side-channel attack called differential-behavior attack and propose several classes of SR-equivalent scan circuits using dummy flip-flops in order to protect the scan-based differential-behavior attack. To show the security level of those extended scan circuits, we introduce differential-behavior equivalent relation, and clarify the number of SR-equivalent extended scan circuits, the number of differential-behavior equivalent classes and the cardinality of those equivalent classes.

This paper presents a multiple weight set weighted random BIST scheme to perform power aware test which takes into account peak power constraint while reducing the overall energy consumption. Generally, exceeding the peak power budget during test provokes problems such as erroneous circuit function due to IR drop and electrical damage to the circuit. On the other hand, excessive power reduction during test can degrade fault screening capability of the test since the test environment becomes substantially less stringent than the environment in which the device is actually used. In this paper we address both these problem simultaneously. The main contribution of this paper is to provide an efficient scan based weighted random BIST scheme within peak power constraint and adequate energy consumption. In order to restrict the amount of test power consumption, fault clustering is performed. The size of the fault cluster is changed to adjust the amount of power consumption. We assume full scan environment, test per scan testing, and single stuck-at fault model. Genetic algorithm (GA) based optimization method is proposed to find effective weight sets.

We reported a secure scan design approach using extended shift registers that are functionally equivalent but not structurally equivalent to shift registers. The security level of the secure scan architecture based on those shift register equivalents is determined by the probability that an attacker can identify the configuration of the shift register equivalent used in the circuit, and hence the attack probability approximates to the reciprocal of the cardinality of the class of shift register equivalents. In this paper, we clarify the cardinality of each class of shift register equivalents from several linear structured circuits and the cardinality of the whole class of shift register equivalents. We also consider the enumeration problem of shift register equivalents and the synthesis problem of desired shift register equivalents. A program called SREEP (Shift Register Equivalents Enumeration and Synthesis Program) is presented to solve those problems.

It has been recognized that the design of similarity measures to compare multiple motion-capture (mocap) data streams is one of the major tasks in human motion analysis [Müller et al. 2008]. The information of similarity is utilized for many applications such as the retrieval of mocap data streams.

This paper proposes an X-fault model for fault diagnosis of physical defects with unknown behaviors by using X symbols. An efficient X-fault simulation method and an efficient X-fault diagnostic reasoning method are presented. Based on these, an X-fault diagnosis method is described to improve the failure analysis for a wide range of physical defects in complex IC circuits.

This paper presents a new approach to improving the diagnosability of a CMOS circuit by dividing it into independent partitions and using a separate power supply for each partition. This technique makes it possible to implement multiple I/sub DDQ/ measurement points. As a result, the diagnosability of the circuit can be improved. The problem of partitioning a circuit is addressed and optimum and heuristic solutions are proposed. The effectiveness of our approach is demonstrated through experimental results.

Temperature can be used as a test observable: some failures when activated produce an increase in local power dissipation, changing the surface thermal map of the IC, being detectable with built-in thermal sensors. In this work, both the feasibility of this testing technique and the generation of the specific test pattern are discussed.

The advantage of random testing is that test application can be performed at a low cost in the BIST scheme. However, not all circuits are random pattern testable. In this paper, we present a method for improving random pattern testability of logic circuits by partial circuit duplication. The basic idea is to detect random pattern resistant faults by using the difference between the duplicated part of a circuit and the original part. Experimental results on benchmark circuits show that high fault coverage can be achieved with a very small amount of hardware overhead.

This paper discusses the problem of locating transistor leakage faults with only I/sub DDQ/ measurement. A new approach of equivalence fault collapsing is proposed for reducing the number of faults that must be considered. Fault location is performed by using both random and deterministic tests in order to obtain a high diagnostic resolution with a small number of tests. The experimental results show that the diagnosed faults are confined to only a few gates in many cases and that a very high average diagnostic resolution can be achieved for a gate-array circuit.