While mining software repositories is a field which has greatly grown over the last ten years, Large Scale Integrated circuit (LSI) design repository mining has yet to reach the momentum of software's. We felt that it represents untouched potential especially for defect prediction. In an LSI, referred to as hardware later on, verification has a high cost compared to design. After studying existing software defect prediction techniques based on repository mining, we decided to adapt some for hardware design repositories in the hope of saving precious resources by focusing design and verification effort on the most defect prone parts of the design. By focusing our resources on the previously mentioned parts, we hope to improve our designs quality. We discuss how we applied these prediction techniques to hardware and show our results are promising for the future of hardware repository mining. Our results allowed us to estimate a possible total verification time reduction of 12%.

In this paper, we present a successful application of a simulation-based sequential Automatic Test Pattern Generation (ATPG) for safety property verification, with the target on verifying safety property of large, industrial strength, hardware designs for which current formal methods fail. Several techniques are developed to increase the effectiveness and efficiency during state exploration and justification of the test generator for verification, including (1) incorporation of a small combinational ATPG engine, (2) reset signal masking, (3) threshold-value simulation, and (4) weighted Hamming distance. Experimental results on both ISCAS89 benchmark circuits and real industry circuits have shown that this simulation-based verifier achieves better or comparable results to current state-of-the-art formal verification tools BINGO and CHAFF.

This paper introduces a new method for manually generating test programs to validate a processor design. Current manual methods do not utilize high level of abstraction for describing test programs and lack many important features like reusability, incremental validation, and test program compaction; they also work on a formal model specifically developed for validation purposes. To solve the above problems, we use test specification expressions to describe test programs and generate test sequences based on an instruction-set description of a processor written for synthesis purposes. We provide experimental results of generating test programs for several processors to show the effectiveness of our method.

A standard design methodology for embedded processors today is the system-on-a-chip design with potentially multiple heterogeneous processing elements on a chip, such as a very long instruction word (VLIW) processor, digital signal processor (DSP), and field-programmable gate array. To be able to program these devices, we need compilers that are capable of generating efficient code for the different types of processing elements with efficiency measured in terms of power, area, and execution time. In addition, the compilers should also be highly retargetable to enable the system designer to quickly evaluate different cores for the application on hand and reduce the time to market. In this paper, we show that we can extend a conventional VLIW compilation environment to develop highly retargetable optimizing compilers for DSPs with irregular architectures. We have used the second generation Fujitsu Hiperion fixed-point DSP as our primary example to evaluate the compiler framework. We demonstrate through experimental results that execution time for the assembly code generated using our framework is roughly two times better than that of the code generated by a widely used commercially available DSP compiler. Even without incorporating DSP-specific optimizations in our extended VLIW framework, we demonstrate that the compiled code has a better performance than the code generated by a commercial DSP-specific compiler in all our examples.

Article Free Access Share on Automatic partitioning for efficient combinatorial verification Authors: Rajarshi Mukherjee Fujitsu Laboratories of America, 595 Lawrence Expressway, Sunnyvale, CA Fujitsu Laboratories of America, 595 Lawrence Expressway, Sunnyvale, CAView Profile , Jawahar Jain Fujitsu Laboratories of America, 595 Lawrence Expressway, Sunnyvale, CA Fujitsu Laboratories of America, 595 Lawrence Expressway, Sunnyvale, CAView Profile , Koichiro Takayama Fujitsu Laboratories of America, 595 Lawrence Expressway, Sunnyvale, CA Fujitsu Laboratories of America, 595 Lawrence Expressway, Sunnyvale, CAView Profile , Masahiro Fujita Fujitsu Laboratories of America, 595 Lawrence Expressway, Sunnyvale, CA Fujitsu Laboratories of America, 595 Lawrence Expressway, Sunnyvale, CAView Profile Authors Info & Claims ASP-DAC '00: Proceedings of the 2000 Asia and South Pacific Design Automation ConferenceJanuary 2000 Pages 67–72https://doi.org/10.1145/368434.368521Published:28 January 2000Publication History 0citation161DownloadsMetricsTotal Citations0Total Downloads161Last 12 Months10Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

We have developed a filter-based framework where several fundamentally different techniques can be combined to provide fully automated and efficient heuristic solutions to verification and possibly other NP-complete problems. Such an integrated methodology is far more robust and efficient than any single existing technique on a wide variety of circuits. Our methodology has been applied to verify the ISCAS 85 benchmark circuits and efficient verification results have been presented on a large set of industrial circuits which could not be verified using several published techniques and commercial verification tools available to us.

Combinational verification is a co-NP complete problem. However, in reality, several techniques exist which perform reasonably well on many practical circuits. Also, it is often found that while one technique efficiently verifies a given circuit it fails badly on another circuit, whereas a certain other technique is efficient on the latter circuit but cannot handle the former circuit. Therefore, clearly, a robust verification methodology cannot depend on any single technique. Our goal in this research is to build a verification methodology whose performance is more immune to circuit variations. We have developed a methodology where several fundamentally different techniques can be combined to provide efficient heuristic solutions to combinational verification, and possibly other intractable problems as well. Such an integrated methodology is far more robust and efficient on a majority of combinational verification problems than any single existing technique. In this paper, we discuss the methodology in detail and present verification results using a fully automated prototype of the proposed methodology. Using this methodology, we can verify many circuits which could not be efficiently verified using any published techniques available to us, and even by some popular commercial combinational verification programs.

For system-level verification of a large-scale design, logic simulation is widely used. When a simulation trace exposes a design error a designer may rectify the design inadequately because the trace shows only one particular erroneous path. This is one of the essential problems of simulation based verification. On the other hand, model checkers are becoming widely used in industry but cannot verify large designs. We propose a new verification methodology based on a "navigated" model checking in order to overcome the above problems. We first generalize the trace and generate a property. We then verify the rectified design against the property by navigating state traversal in model checking. With navigation, we can verify designs without ad-hoc simplification and also can check various possible paths relating the error, instead of concentrating on a particular path of the trace. We have successfully verified bus transactions of a system-on-a-chip having two million transistors with our methodology. For one case, we found that the rectification was inadequate, and we fixed it successfully.

A method is presented to accelerate test generation, which synthesizes a test-generation circuit S(C, F) that combines the original combinational circuit C (modified by programmable faults F) and peripheral circuits that automatically generate a test of C. The test patterns are generated by searching the inputs to expose faults to the outputs using an ultrahigh-speed simulator (SP).>