This paper describes a two-state methodology for register transfer level (RTL) logic simulation in which the use of the X-state is completely eliminated inside ASIC designs. Examples are presented to show the gross pessimism and optimism that occurs with the X in RTL simulation. Random two-state initialization is offered as a way to detect and diagnose startup problems in RTL simulation. Random two-state initialization (a) is more productive than the X-state in gate-level simulation, and (b) provides better coverage of startup problems than X-state in RTL simulation. Consistent random initialization is applied (a) as a way to duplicate a startup state using a slower diagnosisoriented simulator after a faster detection-oriented simulator reports the problem, and (b) to verify that the problem is corrected for that startup state after the design change intended to fix the problem. In addition to combining the earlier ideas of two-state simulation, and random initialization with consistent values across simulations, an original technique for treatment of tri-state Z's arriving into a two-state model is introduced.

An approach is proposed to the prediction, prior to layout, of the paths and nets that will most likely be critical after layout. The approach makes use of the notion of categorization. The parameters that are highly correlated with the total path delay are first identified. These parameters are combined in a single score function. This function is evaluated for each enumerated path. The k paths with the smallest scores (or largest depending on the score function) are the most critical paths. The nets covered by the selected paths are the predicted critical nets. The nets are also ranked according to their coverage frequencies, timing (load factors), and physical characteristics (number of loading pins). A description is given of the delay model used and the authors' approach to the prediction of the dangerous paths and nets. Some experimental results are presented.>