An intelligent partial Gauss-Seidel scheme (PGS) for general circuit simulation is described. This approach is a novel combination of direct solution using incomplete LU factorization, and iterative solution using Gauss-Seidel relaxation. The method converges faster and more reliably than Gauss-Seidel, while taking a comparable amount of execution time per iteration. Reliable analytic rules are derived such that terms that would be relaxed in Gauss-Seidel are relaxed only if they are considered small by applying these rules. Solution speeds up to ten times faster than direct methods have been demonstrated and higher gains are anticipated for larger circuits. This scheme is robust and accurate for circuits with many different element types, including bipolar transistors, MOSFETs, diodes, inductors, and dependent sources.>

The authors investigate a power estimation technique for VLSI that combines the accuracy of simulation-based techniques with the speed of the probabilistic techniques. The resulting method is statistical in nature; it consists of applying randomly generated input patterns to the circuit and monitoring, with a simulator, the resulting power value. This is continued until a value of power is obtained with a desired accuracy, at a specified confidence level. The authors present the algorithm and experimental results, and discuss the superiority of the approach.>

An alternative technique for power estimation that combines the accuracy of simulation-based techniques with the speed of the probabilistic technique is investigated. The resulting method is statistical in nature; it consists of applying randomly-generated input patterns to the circuit and monitoring, with a simulator, the resulting power value. This is continued until a value of power is obtained with a desired accuracy, at a specified confidence level. The algorithm and experimental results are presented and the superiority of this approach is discussed.>

The improvement in computational throughput of VLSI circuit simulation is addressed. A high degree of natural parallelism exists in the circuit simulation problem; potentially a large number of processor can be used efficiently. Three distinct approaches for obtaining parallel execution in direct-method circuit simulators are investigated. These approaches differ primarily in the size of the individual tasks used to obtain parallel execution. The relative advantages of each approach are examined, and performance data from simulations on parallel processing systems are presented. For the third approach, very good parallel efficiency was obtained; in some cases, 99% parallelism has been observed.>

The authors present a general purpose, parallel matrix solver based on the conjugate gradient squared (CGS) method which features a novel preconditioning scheme commensurate with massive parallel computing. The solver algorithm has been successfully used for solving linear systems of equations arising from circuit and device simulations with MOS and bipolar junction transistor (BJT) circuits, both digital and analog, as well as high-level injection conditions in devices. The performance of the algorithm can be further improved by a matrix partitioning scheme.>

A current-estimation approach to support the analysis of electromigration (EM) failures in power supply and ground buses of CMOS VLSI circuits is discussed. It uses the original concept of probabilistic simulation to efficiently generate accurate estimates of the expected current waveform required for electromigration analysis. Thus, the approach is pattern-independent and relieves the designer of the tedious task of specifying logical input waveforms. This approach has been implemented in the program CREST (current estimator) which has shown excellent accuracy and dramatic speedups compared with traditional approaches. The approach and its implementation are described, and the results of numerous CREST runs on real circuits are presented.>

Two techniques for general circuit simulation, an intelligent, partial Gauss-Seidel scheme (PGS) and a preconditioned conjugate-gradient scheme (PLUCGS), are described. Both techniques are robust and accurate for bipolar and MOS analog and digital circuits. PGS is a novel combination of direct solution, using LU factorization, and iterative solution, using Gauss-Seidel relaxation. The method converges faster and more reliably than Gauss-Seidel, while taking a comparable amount of execution time per iteration. Solution speeds up to 6 times faster than direct methods have been demonstrated and higher grains are anticipated for larger circuits. The second method, PLUCGS, uses a partial LU factorization as a preconditioner; a vectorized implementation on a CONVEX C-240 computer is 5-7 times faster than the direct solution method with only one-fourth the memory requirements.>

To exploit time-domain latency in circuit simulation using direct methods, an accurate, computationally efficient model for slowly moving, dormant portions of the circuit is required. A new, implicit integration method, the overdetermined polynomial method (ODPM), has been developed which permits the formulation of an accurate latent model. Using the ODPM integration method, the Jacobian of a dormant subcircuit need not be reevaluated over a large number of time steps of varying size. An accurate Norton equivalent circuit that emulates the impedance and current characteristics of the subcircuit can be obtained without reevaluation of the Jacobian or nonlinear charge computations. This new approach for utilizing latency produces significant improvements in circuit simulation speed with no decrease in accuracy or generality. The authors have demonstrated speed gains of 3 to 20 times over TISPICE for several large circuits.>

An approach for modeling dormant subcircuits is presented that utilizes iteration latency to provide speed improvements that are comparable to the potential speed improvements of an independent time step approach. This scheme minimizes the work required on the first iteration at a time point, which is the normal limiting factor in iteration latency schemes. However, since simulations are performed for each subcircuit at each time point, the penalty for backing up when truncation error is unacceptable is minimized.>

CREST is a pattern-independent current estimation approach developed to support electromigration analysis tools. It uses the powerful, original concept of probabilistic simulation to generate accurate estimates of the expected current waveforms efficiently. The original implementation of CREST is extended to circuits containing pass transistors, reconvergent fanout, and feedback, and heuristics to simulate circuits with large reconvergent fanout or feedback blocks efficiently are provided. The results of using CREST on several real circuits are presented.>