Deep learning has significantly advanced the audio classification, achieving remarkable results. However, these successes often rely on extensive manual annotation of audio, a labor-intensive and costly process. Active Learning (AL) presents a promising solution by minimizing the required amount of annotation through the iterative selection of the most informative audio samples. Current AL methods for audio classification typically depend solely on the latest model checkpoint, overlooking the dynamics of the entire training process. The Complementary Learning Systems (CLS) theory posits that the interplay between short-term and long-term memory systems can effectively measure sample uncertainty, offering a means to capture training dynamics. In this work, we introduce a novel AL framework for audio classification, termed CLS-AL, which addresses the limitations of existing methods by simultaneously maintaining both short-term and long-term memory models. This dual-memory approach allows for a more comprehensive consideration of training dynamics. The divergence in predictions between these memory models provides a new metric for evaluating the uncertainty of unlabeled samples, enhancing the effectiveness of the AL sample selection process. We demonstrate the effectiveness and generalizability of CLS-AL through extensive experiments on a diverse set of audio datasets, showing that CLS-AL obviously outperforms existing state-of-the-art methods.

Predicting the popularity of social media videos involves estimating user engagement based on rich multimodal information embedded within the posts. Unlike static images, videos incorporate temporally evolving visual signals that, alongside associated metadata such as descriptions, hashtags, timestamps, and user attributes, offer valuable insights into their potential audience reach. Prior approaches typically extract features from different modalities independently and merge them via naïve concatenation, which overlooks the semantic discrepancy and interaction dynamics across modalities. To address these limitations, we propose a feature fusion framework that encodes and aligns video content and associated textual cues into a shared semantic space. By jointly modeling temporally structured visual features with context-aware textual embeddings, our method effectively captures cross-modal correlations that are crucial for discerning content virality patterns. In addition, we incorporate user-centric behavioral profiles and content creation dynamics, enriching the representation with personalized signals that reflect audience-specific preferences. Notably, our method achieves top-tier performance in the 2025 SMP challenge, ranking among the highest-performing entries. This strong empirical result underscores the value of deep semantic alignment across video, text, and user domains in accurately forecasting social media video popularity.

Security is one of the top considerations in hardware designs for Internet-of-Things (IoT), where embedded cryptosystems are extensively used. Traditionally, random dynamic voltage scaling technology has been shown to be very effective in improving the resistance of cryptosystems against side-channel attacks. However, in this paper we demonstrate that the resistance can be undermined by providing lower off-chip power supply voltage. In order to address this issue, we then further propose to monitor the off-chip power supply voltage, and trigger an alarm to protect valued information once the power supply voltage is lower than the expected voltage (threshold voltage). However, considering both maintenance cost of IoT devices and the environment noise on power supply voltage, we first formulated this problem as a nonzero sum game model, and the attacker and the circuit supplier (defender) are the players of this game. The analysis of the Nash equilibria in this game show interesting guideline to the defender about the choice of threshold voltage, which is based on parameters of cryptosystem including the value of information, denial-of-service cost in IoT, etc.

A sub-threshold design could provide a compelling approach to power critical applications. An exponential relationship exists, however, between the delay and the threshold voltage, that makes this design-time timing closure extremely difficult, if not impossible, to achieve. Several previous studies were focused on the technique of body biasing during post-silicon tuning for delay compensation. But they were mostly for super-threshold designs where spatially correlated ${L} _{\mathbf {eff}}$ variation dominates. They cannot be applied directly to sub-threshold designs in which purely random threshold voltage variations dominate. These works also assumed multiple body biasing voltage domains and multiple body biasing voltage levels, which involve significant design overhead. The problem of selective body biasing for post-silicon tuning of sub-threshold designs is examined in this paper. The possibility of using only one body bias voltage domain with a single body bias voltage is explored. The problem was formulated first as a linearly constrained statistical optimization model. The adaptive filtering concept from the signal processing community was then adopted so that an efficient, yet novel, solution could be developed. Using several 65 nm industrial designs, experimental results suggest that, compared with a seemingly more intuitive approach, the proposed approach can improve the pass rate by 57% on average with similar standby power and the same number of body biasing gates. This approach can reduce the standby power, on average, by 84%, with a 20% pass rate loss, more than the approach to bias all the gates.

The lack of accurate yet open to public simulation infrastructure has puzzled researchers in the memcomputing area for sometime. In this paper, we propose for the first time a full tool chain called MSim that supports the cycle-accurate microarchitecture level simulation for memcomputing studies. With MSim, the performance gains of utilizing memcomputing for arbitrary applications on user configurable computer system architectures can be evaluated in high accuracy. In addition, MSim provides flexible interfaces with pervasive object-oriented design, which makes it well-suited as a good base platform for researchers to explore new memcomputing technologies.

Retention registers have been widely used in power gated designs to store data during sleep mode. However, their excessive area and leakage power render it imperative to minimize the total retention storage size. The current industry practice replaces all registers with singlebit retention ones, which significantly limits the design freedom and yields suboptimal designs. Toward this, for the first time in the literature, we propose the concept and the design of multibit retention registers, with which only selected registers need to be replaced. The technique can significantly reduce the number of bits that need to be stored and thus the leakage power, but needs several clock cycles for mode transition. In addition, an efficient assignment algorithm is developed to minimize the total retention storage size subject to mode transition latency constraint. Experimental results show that our framework on average can reduce the leakage power in sleep mode by 84% along with additional mode transition latency of 6 to 11 clock cycles, compared with the singlebit retention register-based design.

Retention registers have been widely used in power gated design to store data during sleep mode. Since they consume much larger area and power than normal registers, it is imperative to minimize the total retention storage size. The current industry practice only replace all registers with single-bit retention ones, which significantly limits the design freedom and results in excessive area and power overhead. Towards this, for the first time in literature, we propose the concept of multi-bit retention register, with which only selected registers need to be replaced. It can significantly reduce the number of bits that need to be stored and thus the area and leakage power, but needs several clock cycles for mode transition. In addition, an efficient assignment algorithm is developed to minimize the total retention storage size subject to mode transition latency constraint. Experimental results show that our framework on average can reduce the leakage power in sleep mode and the retention storage area by 66.03%, compared with the single-bit retention register based design.

With the massive deployment of mobile devices and sensor networks, resistance against side-channel attacks in cryptographic systems has become an active research topic in recent years. While various security measures exist in literature, most of them are deterministic in nature, where the same input plaintext always results in the same power trace with a given key. Thus, attackers can still aggregate the small deviations between the power traces to identify the correct key. Towards this, random dynamic voltage scaling has been proposed in the literature, which is demonstrated to be effective against Differential Power Analysis (DPA). In this paper, we evaluate this approach, along with the expanded feature of spatial randomness, to resist Correlation Power Analysis (CPA).

A new iterative learning control method is presented for the trajectory tracking control of linear time-variant systems. This new method does not need detailed knowledge of the controlled system. However, a reference batch is designed, in which some small change of the input trajectory in the current batch is applied to the controlled system, and then its output trajectory is obtained. The ratio of the input change and corresponding output change in the current and reference batch is used as the gain in the learning law for calculating the inputs of the next batch. Thus the method can track the desired trajectory successfully while the iteration is running on. The convergence of the proposed method is analyzed, and the method is validated on a typical linear time-variant system.