Function merging is a pivotal technique for reducing code size by combining identical or similar functions into a single function. While prior research has extensively explored this technique, it has not been assessed in conjunction with function outlining and linker’s identical code folding, despite substantial common ground. The traditional approaches necessitate the complete intermediate representation to compare functions. Consequently, none of these approaches offer a scalable solution compatible with separate compilations while achieving global function merging, which is critical for large app development. In this paper, we introduce our global function merger, leveraging global merge information from previous code generation runs to optimistically create merging instances within each module context independently. Notably, our approach remains sound even when intermediate representations change, making it well-suited for distributed build environments. We present a comprehensive code generation framework that can seamlessly operate both the state-of-the-art global function outliner and our global function merger. These components work in harmony with each other. Our assessment shows that this approach can lead to a 3.5% reduction in code size and a 9% decrease in build time.

Function layout, also known as function reordering or function placement, is one of the most effective profile-guided compiler optimizations. By reordering functions in a binary, compilers can improve the performance of large-scale applications or reduce the compressed size of mobile applications. Although the technique has been extensively studied in the context of large-scale binaries, no study has thoroughly investigated function layout algorithms on mobile applications. In this article, we develop the first principled solution for optimizing function layouts in the mobile space. To this end, we identify two key optimization goals: reducing the compressed code size and improving the cold start-up time of a mobile application. Then, we propose a formal model for the layout problem, whose objective closely matches our goals, and a novel algorithm for optimizing the layout. The method is inspired by the classic balanced graph partitioning problem. We have carefully engineered and implemented the algorithm in an open-source compiler, Low-level Virtual Machine (LLVM). An extensive evaluation of the new method on large commercial mobile applications demonstrates improvements in start-up time and compressed size compared to the state-of-the-art approach. 1

Function layout, also known as function reordering or function placement, is one of the most effective profile-guided compiler optimizations. By reordering functions in a binary, compilers can improve the performance of large-scale applications or reduce the compressed size of mobile applications. Although the technique has been extensively studied in the context of large-scale binaries, no study has thoroughly investigated function layout algorithms on mobile applications.

Positive user experience of mobile apps demands they not only launch fast and run fluidly, but are also small in order to reduce network bandwidth from regular updates. Conventional optimizations often trade off size regressions for performance wins, making them impractical in the mobile space. Indeed, profile-guided optimization (PGO) is successful in server workloads, but is not effective at reducing size and page faults for mobile apps. Also, profiles must be collected from instrumenting builds that are up to 2X larger, so they cannot run normally on real mobile devices.

Inlining is critical for both performance and size in mobile apps. When building large mobile apps, ThinLTO, a scalable link-time optimization is imperative in order to achieve both optimal size and build scalability. However, inlining with ThinLTO is not tuned to reduce the code size because each module inliner works independently without modeling the size cost across modules, and functions are often not eligible to import due to private references, appearing in Objective-C or Swift for iOS. This paper extends the bitcode summary to perform a global inlining analysis to find inline candidates for saving the code size. Using this summary information, a pre-inliner eagerly inlines the candidates that are proven to shrink the size. When the inline candidates are not eligible to import, a pre-merger combines their bitcode modules to remove inline restrictions. Our work improves the size of real-world mobile apps when compared to the MinSize (-Oz) optimization level. We reduced the code size by 2.8% for SocialApp and 4.0% for ChatApp.

Solid-state lighting is a rapidly growing area of research and applications, due to the reliability and predicted high efficiency of these devices. The white LED sources that are typically used for general illumination can also be used for data transmission, and Visible Light Communications (VLC) is a rapidly growing area of research. One of the key challenges is the limited modulation bandwidth of sources, typically several MHz. However, as a room or coverage space would typically be illuminated by an array of LEDs there is the potential for parallel data transmission, and using optical MIMO techniques is potentially attractive for achieving high data rates. In this paper we investigate non-imaging and imaging MIMO approaches: a non-imaging optical MIMO system does not perform properly at all receiver positions due to symmetry, but an imaging based system can operate under all foreseeable circumstances. Simulations show such systems can operate at several hundred Mbit/s, and up to Gbit/s in many circumstances.

A key analysis developed for the compilation of parallel programs is thread escape analysis (hereafter referred to as escape analysis), which determines what objects are accessed in more than one thread, and which references within a program are references to such objects. Escape analysis has several important client optimizations: identifying objects on which races may exist, identifying locks that can be removed, identifying heap allocated objects referenced within a single thread, and compiling for strict memory models. While the effectiveness of individual escape analyses has been measured for different client optimizations, there has been no effort to compare the effectiveness of the different escape analyses over all the different clients. Nor has therebeen any attempt to develop a perfect escape analysis and measure how far from it the different escape analyses are. This paper presents a perfect escape analysis for specific runs of Java programs, which tracks all possibly escaping objects at runtime, and determines precisely which ones escape. It uses a caching technique to reduce the time and space needed for collecting access information by 8 times and 48 times, respectively, relative to not using the caching technique. We compare the perfect escape analysis results with the results from the practical escape analyses, using the four clients above or metrics that are significant for those clients. From this comparison we conclude that the relative precision of different escape analyses changes with different clients and that the most precise analysis for each client is "close enough" to the perfect analysis for three out of the four clients.

Thread escape analysis conservatively determines which objects may be accessed in more than one thread. Thread escape analysis is useful for a variety of purposes—finding races in multi-threaded programs, removing useless synchronization, allocating data to thread-local heaps, and compiling to target more strict consistency models. Thread escape analyses are often interprocedural, and interprocedural analyses are generally either too slow to perform at runtime in dynamic systems, or trade-off significant amounts of precision for speed. This paper describes a two-phase offline/online interprocedural and inter thread escape analysis that is faster and more accurate, on average, than previously published analyses. By performing an offline pre-analysis followed by a dynamic online analysis that integrates offline results with dynamic information, significant improvements in performance and accuracy are achieved. For compiling Java programs under a sequentially consistent memory model, our approach enables application executions that are, on average, 1.5 times faster than those using the previous fastest online algorithm, with only 80% of the online compilation time.

This paper presents the design and implementation of a sliding memory plane (SliM) image processor chip to build a mesh-connected SIMD architecture called a SliM array processor. The SliM image processor chip consists of 5/spl times/5 processing elements (PEs) connected by a mesh topology. A set of SliM image processor chips can form the SliM array processor. Due to the idea of sliding, that is, overlapping inter-PE communication with computation, the SliM image processor can greatly reduce the inter-PE communication overhead, a significant disadvantage of existing SIMD array processors. In addition, using the by-passing path provides eight-way connectivity even with four physical links. This paper addresses architectures of the SliM image processor chip, the design of an instruction set, and implementation issues. The chip has 55255 gates and twenty-five 128/spl times/9-bit SRAM modules, and was simulated at 18 MHz for the worst case conditions, and will actually run at a higher clock rate. The package type is the 144 pin MQFP. We conduct the performance evaluation of the chip that shows a significant improvement.