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Jing Yu 0026

dblp:42/6466-26 · DBLP profile ↗
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4ranked-venue papers
0as first author
4since 2021 · last 2026
0009-0003-0694-1741ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 2 · 2 since 2021Systems, architecture and hardware · 1 · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Artificial intelligence
1 paper
Efficient and distributed learning · 67% Language models and text generation · 33%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 100%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Machine learning › Efficient and distributed learning
inference efficiency
1.012026
HitKV: Activation Frequency Knows Which Tokens Are Important · AAAI 2026
Machine learning › Efficient and distributed learning › KV cache management
KV cache compression
1.012026
HitKV: Activation Frequency Knows Which Tokens Are Important · AAAI 2026
Natural language and speech › Language models and text generation › language modeling › long-context language modeling › context utilization
long-context modeling
1.012026
HitKV: Activation Frequency Knows Which Tokens Are Important · AAAI 2026
Memory systems
cache
0.912025
LAShards: Low-Overhead and Self-Adaptive MRC Construction for Non-Stack Algorithms · IEEE Trans. Computers 2025
Memory systems › cache management
cache replacement
0.912025
LAShards: Low-Overhead and Self-Adaptive MRC Construction for Non-Stack Algorithms · IEEE Trans. Computers 2025
Memory systems › cache management
shared cache management
0.312025
LAShards: Low-Overhead and Self-Adaptive MRC Construction for Non-Stack Algorithms · IEEE Trans. Computers 2025

Methods — techniques the papers use, named apart from their topics

layer-aware memory allocation · 1.0attention scoring · 1.0spatially hashed sampling · 0.9miniature simulation · 0.9locality-aware sampling · 0.9
YearPublicationVenuePosition
2026 HitKV: Activation Frequency Knows Which Tokens Are Important
abstract
The demand for long-context processing in large language models (LLMs) continues to escalate alongside rapid advancements in their capabilities. However, the intermediate attention keys and values (KV cache) employed to avoid re-computations, also grow linearly with sequence length, far exceeding the memory capacity of consumer-grade GPUs. Consequently, many studies have proposed KV cache compression methods that evict unimportant tokens based on variant attention scoring strategies. These methods typically retain the KV pairs of the top-k scoring tokens under a fixed memory budget. However, they still face several limitations. First, they disregard the activation frequency of tokens, specifically the count of times tokens achieve top-k scores in the attention distribution of following tokens. The methods based on variant attention scores may incorrectly evict some high-activation-frequency yet low final-scoring tokens. Second, the activation frequency exhibits different distribution patterns across layers and tasks. Neglecting these differences negatively impacts model performance and task adaptability. Our analysis of the actual token activation frequency and its unique characteristics across layers and task types reveals potential opportunities to address these issues. In this paper, we propose HitKV, which employs hit rates to directly characterize token activation frequencies, enabling adaptive layer-aware and task-aware KV cache eviction under the uniform memory allocation strategies. Also, HitKV can be easily integrated into layer-specific memory allocation methods. Experimental results demonstrate that HitKV maintains model performance with preserving only 3% of the KV cache, achieves high-quality generation outputs in long-text generation tasks, and delivers 4× throughput improvement over baselines.
Sanle Zhao, Yujuan Tan, Jing Yu 0026, Zhuoxin Bai, Zongjie Wang, Ao Ren
AAAI3
2025 RobTrack: A Robust 3D Multi-object Tracking Method for Edge Devices
Mingrui Qiang, Ao Ren, Yujuan Tan, Jing Yu 0026, Zhuoxin Bai, Duo Liu 0002, Kan Zhong, Chaoxia Qin
ICIC (5)4
2025 YOLOCS: Object detection based on dense channel compression for feature spatial solidification
Weisheng Li 0001, Yujuan Tan, LinLin Shen, Jing Yu 0026, Haojie Fu
Knowl. Based Syst.5
2025 LAShards: Low-Overhead and Self-Adaptive MRC Construction for Non-Stack Algorithms
abstract
Shared cache systems have become increasingly crucial, especially in cloud services, where the Miss Ratio Curve (MRC) is a widely used tool for evaluating cache performance. The MRC depicts the relationship between the cache miss ratio and cache size, indicating how cache performance trends with varying cache sizes. Recent advancements have enabled efficient MRC construction for stack replacement policies. For non-stack policies, miniature simulation downsizes the actual cache size and data stream through spatially hashed sampling, providing a general method for MRC construction. However, this approach still faces significant challenges. Firstly, constructing an MRC requires numerous mini-caches to obtain miss ratios, consuming significant cache resources, leading to tremendous memory and computing overhead. Secondly, it cannot adapt to the dynamic I/O workloads, resulting in less precise MRC.To address these issues, we propose LAShards, a low-overhead and self-adaptive MRC construction method for non-stack replacement policies. The key idea behind LAShards is to exploit the locality and burstiness in access patterns. It can statically reduce memory usage and dynamically adapt to workloads. Compared to previous works, LAShards can save up to 20× of memory resources, and increase throughput by up to 10×.
Sanle Zhao, Yujuan Tan, Zhaoyang Zeng, Jing Yu 0026, Zhuoxin Bai, Ao Ren, Xianzhang Chen, Duo Liu 0002
IEEE Trans. Computers4