Continuing improvements in semiconductor density are enabling new classes of System-on-a-Chip architectures that combine extensive processing logic and high-density memory. Many of the capabilities of these architectures can be custom tailored to the demands of real-time image processing. This paper identifies and describes candidate computing in memory architectures, and evaluates their performance on several image-processing algorithms.

Information on the behavior of programs is essential for deciding the number and nature of functional units in high performance architectures. In this paper, we present studies on the balance of access and computation tasks on a typical RISC architecture, the MIPS. The MIPS programs are analyzed to find the demands they place on the memory system and the floating point or integer computation units. A balance metric that indicates the match of accessing power to computation power is calculated. It is observed that many of the SPEC floating point programs and kernels from supercomputing applications typically considered as computation intensive programs, place extensive demands on the memory system in terms of memory bandwidth. Access related instructions are seen to dominate most instruction streams. We discuss how these instruction stream characteristics can limit the instruction issue in superscalar processors. The properties of the dynamic instruction mix are used to alert computer architects to the importance of memory bandwidth. Single instruction stream parallelism will not be much greater than two if memory bandwidth is only one. A decoupled access/execute architecture with multiple load/store units and queues which alleviate the balance problem is presented.>

Decoupled computer architectures attempt to achieve superscalar performance by exploiting the fine-grain parallelism between the data access and data execute tasks of a computer program. In this paper, we examine the major bottlenecks in the performance of decoupled architectures. These consist of the load unbalance between the access and execute processors, the limited access processor's instruction issue rate, and the memory bandwidth. We introduce a decoupled architecture that (1) eliminates the access processor's instruction issue bottleneck by reducing the number of data access instructions, and (2) reduces the effects of the memory bandwidth by allowing better data prefetching. The architecture employs special data access mechanisms that take advantage of the regularity of structure data's storage.

In interleaved memories, interference between concurrently active vector streams results in memory bank conflicts and reduced bandwidth. In this paper, we present two schemes for reducing inter-vector interference. First, we propose a memory module partitioning technique in which disjoint access sets are created for each of the concurrent vectors. Various properties of the involved address mapping are presented. Then we present an interlaced data placement scheme, where the simultaneously accessed vectors are interlaced and stored to the memory. Performance of the two schemes are evaluated by trace driven simulation. It is observed that the schemes have significant merit in reducing the interference in interleaved memories and increasing the effective memory bandwidth. The schemes are applicable to memory systems for superscalar processors, vector supercomputers and parallel processors.

Decoupled computer architectures partition the memory access and execute functions in a computer program and achieve high performance by exploiting the fine-grain parallelism between the two. These ar-chitectures make use of an access processor to perform the data fetch ahead of demand by the execute process and hence are often less sensitive to memory access de-lays than conventional architectures, Past performance studies of decoupled computers used memory systems that are interleaved or pipelined. We undertake a sim-ulation study of the latency effects in decoupled com-puters when connected to a single, conventional, non-interleaved data memory module so that the effect of decoupling is isolated from the improvement caused by interleaving. We compare decoupled computer perfor-mance to single processors with caches, study the mem-ory latency sensitivity of the decoupled systems, and also perform simulations to determine the significance of data caches in a decoupled computer architecture. The Lawrence Livermore Loops and two signal process-ing algorithms are used as the simulation benchmark.

Decoupled computer architectures partition the memory access and execute functions in a computer program and achieve high performance by exploiting the fine-grain parallelism between the two. These architectures make use of an access processor to perform the data fetch ahead of demand by the execute process and hence are often less sensitive to memory access delays than conventional architectures. Past performance studies of decoupled computers used memory systems that are interleave or pipelined. We undertake a simulation study of the latency effects in decoupled computers when connected to a single, conventional non-interleaved data memory module so that the effect of decoupling is isolated from the improvement caused by interleaving. We compare decoupled computer performance to single processors with caches, study the memory latency sensitivity of the decoupled systems, and also perform simulations to determine the significance of data caches in a decoupled computer architecture. The Lawrence Livermore Loops and two signal processing algorithms are used as the simulation benchmark.

The speed disparity between processor and memory subsystems has been bridged in many existing large-scale scientific computers and microprocessors with the help of instruction buffers or instruction caches. In this paper we classify these buffers into traditional instruction buffers, conventional instruction caches and prefetch queues, detail their prominent features, and evaluate the performance of buffers in several existing systems, using trace driven simulation. We compare these schemes with a recently proposed queue-based instruction cache memory. An implementation independent performance metric is proposed for the various organizations and used for the evaluations. We analyze the simulation results and discuss the effect of various parameters such as prefetch threshold, bus width and buffer size on performance.

A general model of a memory-based finite-state machine architecture is introduced, the 2k− decision machine (2k− D). The classical (2n− D) and binary decision (2 − D) architectures are shown to be special cases of the 2k− D architecture. The equivalence among the 2k− D solutions for different values of k follows from the sequentialization principle, which is stated in the paper. A cost measure is defined in terms of memory size and a procedure to determine the 2k− D architecture which offers the minimum cost, given that the speed is equal to one state transition per clock cycle, is presented. It is shown that this architecture is not in general the minimum cost solution when the speed of the circuit is not a critical design factor. Also discussed, are the optimization problems to be solved when a minimum cost 2k− D architecture is desired. In addition, bounds on the cost of the 2k− D architecture are calculated in terms of simple measures taken from the mathematical model describing the behavior of the state machine. The results of this research are particularly attractive when LSI and VLSI technologies are considered. State machines constitute fundamental blocks in systems to be fabricated as integrated circuits. Memory-based implementations offer a short design time, regularity of structure, and expandability.

Recently, a good deal of research has been conducted on the use of transition-or edge-sensitive elements in the design of asynchronous sequential circuits. Transition-sensitive memory elements have been used extensively in the implementation of synchronous sequential circuits as a means of eliminating the restrictions placed on pulsewidth. Several means are available for achieving multiple-input or universal transition-sensitive flip-flops. Here the approach is to employ a basic flip-flop as the memory element and add transition-sensitive gating to the flip-flop input. In this manner, any type of transition-sensitive flip-flop may be configured.

A circuit for generating a clock pulse for asynchronous circuits is given, and when used with transition sensitive flip-flops eliminates critical races for an arbitrary state assignment. Thus the minimum number of internal variables may be used. Furthermore, logic and sequential hazards will not affect the circuit performance.

This correspondence shows that the Necula [1] and Slagle, Chang. and Lee [2] methods for determining prime implicants are a mechanization of a method first given by Nelson [3], i. e., generating of all prime implicants by direct expansion of a conjunctive form to a disjunctive form.

Certain partitions in Tracey's assignment method may be eliminated because of impossible transitions on the inputs. This may reduce the complexity of the sequential machine.