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The notion of design for manufacturability is blurring the separation between the tasks of design and manufacture. In the era of nano-technologies, the description of the design rules has retreated back to an early stage form of many conditional cases and even an art. Thus, it is important to set the metrics for the manufacturability. However, who is going to be held accountable for the final outcomes? Should the designer, the EDA developer, the manufacture engineer, or a new breed of experts take the lead to tackle the problem?

With process technology and functional integration advancing steadily, chips are continuing to grow in area while critical dimensions are shrinking. This has led to the emergence of on-chip inductance to be a factor whose effect on performance and on signal integrity has to be managed by chip designers and has to be sometimes traded off against other performance parameters. In this paper, we cover several techniques to reduce on-chip inductance which in turn improve timing predictability and reduce signal delay and crosstalk noise. We present experimental results obtained from simulations of a typical high performance bus structure and a clock tree structure to examine the effectiveness of some of the different inductance reduction techniques.

Many physical synthesis tools interdigitate signal and power lines to reduce cross-talk, and thus, improve signal integrity and timing predictability. Such approaches are extremely effective at reducing cross-talk at circuit speeds where inductive effects are inconsequential. In this paper, we use a detailed distributed RLC model to show that inductive cross-talk effects are substantial in long busses associated with 0.18 micron technology. Simulation experiments are then used to demonstrate that cross-talk in such high speed technologies is much better controlled by re-deploying interdigitated power lines to perform differential signaling.

In this paper we presen t a rank-one update method for updating reduced-order models of interconnect parasitics when driv e resistances or load capacitances change, as commonly occurs during timing analysis. These rank-one updates are extremely inexpensive, do not require reexamining the original in terconnect netw ork, and most importantly are provably equivalent to rereducing the original netw ork. This abstract con tains the proof only for the case of varying the driver resistance, but examples are given to show that the exactness holds more generally. In particular, a cross-talk case is examined where the conductance matrix is singular.

The automation of the design of electronic systems and circuits [electronic design automation (EDA)] has a history of strong innovation. The EDA business has profoundly influenced the integrated circuit (IC) business and vice-versa. This paper reviews the technologies, algorithms, and methodologies that have been used in EDA tools and the business impact of these technologies. In particular, we focus on four areas that have been key in defining the design methodologies over time: physical design, simulation/verification, synthesis, and test. We then look briefly into the future. Design will evolve toward more software programmability or some other kind of field configurability like field programmable gate arrays (FPGAs). We discuss the kinds of tool sets needed to support design in this environment.

This paper describes a HDL synthesis based design methodology that supports user adoption of behavioral-level synthesis into normal design practices.The use of these techniques increases understanding of the HDL descriptions before synthesis, and makes the comparison of pre-and post-synthesis design behavior through simulation much more direct.This increases user confidence that the specification does what the user wants, i.e. that the synthesized design matches the specification in the ways that are important to the user.At the same time, the methodology gives the user a powerful set of tools to specify complex interface timing, while preserving a user's ability to delegate decision-making authority to software in those cases where the user does not wish to restrict the options available to the synthesis algorithms. OverviewThis paper describes a synthesis methodology that uses high-level synthesis (HLS) of behavioral hardware-description language (HDL) descriptions.HLS has the distinguishing characteristic that operations are automatically scheduled, i.e. assigned to states, as opposed to lower-level synthesis, in which operations are assigned to states by the user [1, 2, 3].For example, in an HDL description of a square root function, an operand x would be loaded, a series of operations would follow, and a single result r would be returned.The read x and the write r might be fixed to particular states or times by a communication protocol, but the internal operations that compute the square root would be automatically scheduled.A prospective user of HLS will then ask a number of questions.These will likely include the following:• How can I constrain I/O operations to fall into particular cycles, or range of cycles, to meet existing protocols?• How can I constrain I/O operations to have particular timing relationships?For example, how can I constrain a data ready strobe to be synchronous with data on data ports?• How can I be confident that my interface timing specification really works with the surrounding hardware?• How can I give the scheduling software optimization opportunities when my timing specification is not rigid?For example, I might not care exactly when data was transferred, as long as a corresponding strobe remains synchronized with the data.Thus the strobe and data should be locked together, but the locked strobe/ data pair of operations could move.

Article Scheduling using behavioral templates Share on Authors: Tai Ly Synopsys Inc., 700B E. Middlefield Road, Mountain View, CA Synopsys Inc., 700B E. Middlefield Road, Mountain View, CAView Profile , David Knapp Synopsys Inc., 700B E. Middlefield Road, Mountain View, CA Synopsys Inc., 700B E. Middlefield Road, Mountain View, CAView Profile , Ron Miller Synopsys Inc., 700B E. Middlefield Road, Mountain View, CA Synopsys Inc., 700B E. Middlefield Road, Mountain View, CAView Profile , Don MacMillen Synopsys Inc., 700B E. Middlefield Road, Mountain View, CA Synopsys Inc., 700B E. Middlefield Road, Mountain View, CAView Profile Authors Info & Claims DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation ConferenceJanuary 1995 Pages 101–106https://doi.org/10.1145/217474.217514Published:01 January 1995 52citation351DownloadsMetricsTotal Citations52Total Downloads351Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access