Demo Data from VLDB 2026 / reviewers in the wild / expert
Zilong Wang 0004
dblp:42/898-4
· DBLP profile ↗
6ranked-venue papers
0as first author
0since 2021 · last 2016
—ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 5Theory of computation · 4
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Theoretical computer science
1 paper |
Automated reasoning and model checking · 100% | |
| Software engineering, system software, and programming languages
1 paper |
Concurrent programming · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Concurrent programming › concurrency models › asynchronous programming
asynchronous programs |
0.2 | 1 | 2015 | Bbs: A Phase-Bounded Model Checker for Asynchronous Programs · CAV (1) 2015 |
Automated reasoning and model checking › model checking
bounded model checking |
0.2 | 1 | 2015 | Bbs: A Phase-Bounded Model Checker for Asynchronous Programs · CAV (1) 2015 |
Automated reasoning and model checking
model checking |
0.2 | 1 | 2015 | Bbs: A Phase-Bounded Model Checker for Asynchronous Programs · CAV (1) 2015 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2016 | LLSPLAT: Improving Concolic Testing by Bounded Model CheckingabstractFor software testing, concolic testing reasons about data symbolically but enumerates program paths. The existing concolic technique enumerates paths sequentially, leading to poor branch coverage in limited time. In this paper, we improve concolic testing by bounded model checking (BMC). During concolic testing, we identify program regions that can be encoded by BMC on the fly so that program paths within these regions are checked simultaneously. We have implemented the new algorithm on top of KLEE and called the new tool LLSPLAT. We have compared LLSPLAT with KLEE using 10 programs from the Windows NT Drivers Simplified and 88 programs from the GNU Coreutils benchmark sets. With 3600 second testing time for each program, LLSPLAT provides on average 13% relative branch coverage improvement on all 10 programs in the Windows drivers set, and on average 16% relative branch coverage improvement on 80 out of 88 programs in the GNU Coreutils set. Min Gao 0003, Lei He 0001, Rupak Majumdar, Zilong Wang 0004 |
SCAM | 4 |
| 2015 | Bbs: A Phase-Bounded Model Checker for Asynchronous Programs
Rupak Majumdar, Zilong Wang 0004 |
CAV (1) | 2 |
| 2014 | Kuai: A model checker for software-defined networksabstractIn software-defined networking (SDN), a software controller manages a distributed collection of switches by installing and uninstalling packet-forwarding rules in the switches. SDNs allow flexible implementations for expressive and sophisticated network management policies. We consider the problem of verifying that an SDN satisfies a given safety property. We describe Kuai, a distributed enumerative model checker for SDNs. Kuai takes as input a controller implementation written in Murphi, a description of the network topology (switches and connections), and a safety property, and performs a distributed enumerative reachability analysis on a cluster of machines. Kuai uses a set of partial order reduction techniques specific to the SDN domain that help reduce the state space dramatically. In addition, Kuai performs an automatic abstraction to handle unboundedly many packets traversing the network at a given time and unboundedly many control messages between the controller and the switches. We demonstrate the scalability and coverage of Kuai on standard SDN benchmarks. We show that our set of partial order reduction techniques significantly reduces the state spaces of these benchmarks by many orders of magnitude. In addition, Kuai exploits large-scale distribution to quickly search the reduced state space. Rupak Majumdar, Sai Deep Tetali, Zilong Wang 0004 |
FMCAD | 3 |
| 2013 | Expand, Enlarge, and Check for Branching Vector Addition Systems
Rupak Majumdar, Zilong Wang 0004 |
CONCUR | 2 |
| 2013 | Static Provenance Verification for Message Passing Programs
Rupak Majumdar, Roland Meyer 0001, Zilong Wang 0004 |
SAS | 3 |
| 2010 | Systematic testing for control applicationsabstractAbstract—Software controllers for physical processes are at the core of many safety-critical systems such as avionics, automotive engine control, and process control. Despite their importance, the design and implementation of software controllers remains an art form; dependability is generally poor, and the cost of verifying systems is prohibitive. We illustrate the potential of applying program analysis tools on problems in controller design and implementation by focusing on concolic execution, a technique for systematic testing for software. In particular, we demonstrate how a concolic execution tool can be modified to automatically analyze controller implementations and (a) produce test cases achieving a coverage goal, (b) synthesize ranges for controller variables that can be used to allocate bits in a fixed-point implementation, and (c) verify robustness of an implementation under input uncertainties. We have implemented these algorithms on top of the Splat test generation tool and have carried out preliminary experiments on control software that demonstrates feasibility of the techniques. I. Rupak Majumdar, Indranil Saha 0001, Zilong Wang 0004 |
MEMOCODE | 3 |