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Thomas C. Bartee

dblp:42/9461 · DBLP profile ↗
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4ranked-venue papers
4as first author
0since 2021 · last 1965
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-authorTheory of computation · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Theoretical computer science
2 papers
Coding theory · 100%
Computer architecture, parallel and distributed computing, and storage systems
2 papers
Integrated circuit design · 76% Electronic design automation · 24%

Topics — the 9 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
digital circuit design
0.011965
Design of an Accumulator for a General Purpose Computer · IEEE Trans. Electron. Comput. 1965
Coding theory
finite fields
0.011963
Computation with Finite Fields · Inf. Control. 1963
Integrated circuit design › digital logic
logic gate
0.011965
Design of an Accumulator for a General Purpose Computer · IEEE Trans. Electron. Comput. 1965
Electronic design automation
logic synthesis
0.011961
Computer Design of Multiple-Output Logical Networks · IRE Trans. Electron. Comput. 1961
Integrated circuit design › digital circuit design › logic gate design
NOR gate logic
0.011965
Design of an Accumulator for a General Purpose Computer · IEEE Trans. Electron. Comput. 1965
Coding theory › error-correcting codes › cyclic codes
BCH codes
0.011962
An electronic decoder for Bose-Chaudhuri-Hocquenghem error-correcting codes · IRE Trans. Inf. Theory 1962
Coding theory › decoder design
decoder implementation
0.011962
An electronic decoder for Bose-Chaudhuri-Hocquenghem error-correcting codes · IRE Trans. Inf. Theory 1962
Coding theory
error-correcting codes
0.011962
An electronic decoder for Bose-Chaudhuri-Hocquenghem error-correcting codes · IRE Trans. Inf. Theory 1962
Integrated circuit design › digital circuit design
combinational logic
0.011961
Computer Design of Multiple-Output Logical Networks · IRE Trans. Electron. Comput. 1961

Methods — techniques the papers use, named apart from their topics

minimization criteria · 0.0logic minimization · 0.0finite field arithmetic · 0.0computer-aided design · 0.0carry bridging · 0.0
YearPublicationVenuePosition
1965 Design of an Accumulator for a General Purpose Computer
abstract
This paper describes the logical design of an accumulator register for a general purpose digital computer. The only logic gates used are NOR gates and inverter gates and the sole storage device is a gated clocked flip-flop which takes the value on a single input line when the gate line is high. The accumulator register operates in conjunction with another register called the memory exchange register. The memory exchange register can be added to the accumulator, subtracted from the accumulator, ANDed with, and ORed with the accumulator; the result in each case being placed in the accumulator. The accumulator can also be shifted right or left. The problem of carry propagation during addition is alleviated by carry bridging. The accumulator circuitry has been made simpler by treating the operations to be performed collectively rather than individually, and by careful assignment of input-values to the storage devices.
Thomas C. Bartee, D. J. Chapman
IEEE Trans. Electron. Comput.1
1963 Computation with Finite Fields
Thomas C. Bartee, David I. Schneider
Inf. Control.1
1962 An electronic decoder for Bose-Chaudhuri-Hocquenghem error-correcting codes
Thomas C. Bartee, David I. Schneider
IRE Trans. Inf. Theory1
1961 Computer Design of Multiple-Output Logical Networks
abstract
An important step in the design of digital machines lies in the derivation of the Boolean expressions which describe the combinational logical networks in the system. Emphasis is generally placed upon deriving expressions which are minimal according to some criteria. A computer program has been prepared which automatically derives a set of minimal Boolean expressions describing a given logical network with multiple-output lines. The program accepts punched cards listing the in-out relations for the network, and then prints a list of expressions which are minimal according to a selected one of three criteria. This paper describes the basic design procedure and the criteria for minimality.
Thomas C. Bartee
IRE Trans. Electron. Comput.1