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Vincent van der Leest

dblp:42/9852 · DBLP profile ↗
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7ranked-venue papers
2as first author
0since 2021 · last 2015
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 1 first-authorSecurity and privacy · 3 · 1 first-authorSoftware engineering, systems software and programming languages · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
4 papers
Hardware security and side channels · 70% Cryptographic primitives and cryptanalysis · 30%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware security and side channels › hardware security primitives
physical unclonable function
0.742015
Intelligent Voltage Ramp-Up Time Adaptation for Temperature Noise Reduction on Memory-Based PUF Systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015
Secure Key Generation from Biased PUFs · CHES 2015
Soft Decision Error Correction for Compact Memory-Based PUFs Using a Single Enrollment · CHES 2012
Cryptographic primitives and cryptanalysis
key generation
0.532015
Intelligent Voltage Ramp-Up Time Adaptation for Temperature Noise Reduction on Memory-Based PUF Systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015
Secure Key Generation from Biased PUFs · CHES 2015
Soft Decision Error Correction for Compact Memory-Based PUFs Using a Single Enrollment · CHES 2012
Hardware security and side channels › hardware security primitives › physical unclonable function
memory-based PUF
0.212015
Intelligent Voltage Ramp-Up Time Adaptation for Temperature Noise Reduction on Memory-Based PUF Systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015
Hardware security and side channels › hardware security primitives › physical unclonable function
error correction
0.112012
Soft Decision Error Correction for Compact Memory-Based PUFs Using a Single Enrollment · CHES 2012
Hardware security and side channels › hardware security primitives › physical unclonable function
reconfigurable PUF
0.112011
Recyclable PUFs: Logically Reconfigurable PUFs · CHES 2011
Integrated circuit design
low-power circuit design
0.112015
Intelligent Voltage Ramp-Up Time Adaptation for Temperature Noise Reduction on Memory-Based PUF Systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015
Cryptographic primitives and cryptanalysis › key generation
PUF-based key generation
0.012012
Soft Decision Error Correction for Compact Memory-Based PUFs Using a Single Enrollment · CHES 2012

Methods — techniques the papers use, named apart from their topics

error-correcting codes · 0.4circuit simulation · 0.4key generation · 0.2PUF · 0.2soft decision error correction · 0.1single enrollment · 0.1
YearPublicationVenuePosition
2015 Secure Key Generation from Biased PUFs
Roel Maes, Vincent van der Leest, Erik van der Sluis, Frans M. J. Willems
CHES2
2015 Intelligent Voltage Ramp-Up Time Adaptation for Temperature Noise Reduction on Memory-Based PUF Systems
abstract
The efficiency and cost of silicon physically unclonable function (PUF)-based applications, and in particular key generators, are heavily impacted by the level of reproducibility of the bare PUF responses (PRs) under varying operational circumstances. Error-correcting codes (ECCs) can be used to achieve near-perfect reliability, but come at a high implementation cost especially when the underlying PUF is very noisy. When designing a PUF-based key generator, a more reliable PUF will result in a less complex ECC decoder and a smaller PUF footprint, and hence, an overall more efficient implementation. This paper proposes novel insight and resulting method for reducing noise on memory-based PRs, based on adapting supply voltage ramp-up time to ambient temperature. Circuit simulations on 45 nm low-power CMOS, as well as silicon measurements are presented to validate the proposed method. Our results demonstrate that choosing an appropriate voltage ramp-up for enrollment and adapting it according to the ambient temperature at key-reconstruction is a powerful method which makes memory-based PR noise up to 3× smaller. In addition, this paper investigates the competitiveness of integrating the proposed method in a commercial product; the investigation is done in two phases. First by determining the saved area, and second by implementing a circuit that maps the ambient temperature into an appropriate voltage ramp-up. The results show that the new system costs up to 82.1% less area while it delivers up to 3× higher reproducibility.
Mafalda Cortez, Said Hamdioui, Ali Kaichouhi, Vincent van der Leest, Roel Maes, Geert Jan Schrijen
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.4
2013 Anti-counterfeiting with hardware intrinsic security
abstract
Counterfeiting of goods and electronic devices is a growing problem that has a huge economic impact on the electronics industry. Sometimes the consequences are even more dramatic, when critical systems start failing due to the use of counterfeit lower quality components. Hardware Intrinsic security (i.e. security systems built on the unique electronic fingerprint of a device) offers the potential to reduce the counterfeiting problem drastically. In this paper we will show how Hardware Intrinsic Security (HIS) can be used to prevent various forms of counterfeiting and over-production. HIS technology can also be used to bind software or user data to specific hardware devices, which provides additional security to both soft- and hardware vendors as well as consumers using HIS-enabled products. Besides showing the benefits of HIS, we will also provide an extensive overview of the results (both scientific and industrial) that Intrinsic-ID has achieved studying and implementing HIS.
Vincent van der Leest, Pim Tuyls
DATE1
2012 Soft Decision Error Correction for Compact Memory-Based PUFs Using a Single Enrollment
Vincent van der Leest, Bart Preneel, Erik van der Sluis
CHES1
2012 Comparative analysis of SRAM memories used as PUF primitives
abstract
In this publication we present the results of our investigations into the reliability and uniqueness of Static Random Access Memories (SRAMs) in different technology nodes when used as a Physically Unclonable Function (PUF). The comparative analysis that can be found in this publication is the first ever of its kind, using different SRAM memories in technologies ranging from 180nm to 65nm. Each SRAM memory presents a unique and unpredictable start-up pattern when being powered up. In order to use an SRAM as a PUF in an application, the stability of its start-up patterns needs to be assured under a wide variety of conditions such as temperature and applied voltage. Furthermore the start-up patterns of different memories must be unique and contain sufficient entropy. This paper presents the results of tests that investigate these properties of different SRAM memory technology nodes. Furthermore, it proposes the construction of a fuzzy extractor, which can be used in combination with the tested memories for extracting secure cryptographic keys.
Geert Jan Schrijen, Vincent van der Leest
DATE2
2011 Recyclable PUFs: Logically Reconfigurable PUFs
Stefan Katzenbeisser 0001, Ünal Koçabas, Vincent van der Leest, Ahmad-Reza Sadeghi, Geert Jan Schrijen, Heike Schröder, Christian Wachsmann
CHES3
2011 Evaluation of 90nm 6T-SRAM as Physical Unclonable Function for secure key generation in wireless sensor nodes
abstract
Due to the unattended nature of WSN (Wireless Sensor Network) deployment, each sensor can be subject to physical capture, cloning and unauthorized device alteration. In this paper, we use the embedded SRAM, often available on a wireless sensor node, for secure data (cryptographic keys, IDs) generation which is more resistant to physical attacks. We evaluate the physical phenomenon that the initial state of a 6T-SRAM cell is highly dependent on the process variations, which enables us to use the standard SRAM circuit, as a Physical Unclonable Function (PUF). Important requirements to serve as a PUF are that the start-up values of an SRAM circuit are uniquely determined, unpredictable and similar each time the circuit is turned on. We present the evaluation results of the internal SRAM memories of low power ICs as PUFs and the statistical analysis of the results. The experimental results prove that the low power 90nm commercial 6T-SRAMs are very useful as a PUF. As far as we know, this is the first work that provides an extensive evaluation of 6T-SRAM-based PUF, at different environmental, electrical, and ageing conditions to representing the typical operating conditions of a WSN.
Georgios N. Selimis, Mario Konijnenburg, Maryam Ashouei, Jos Huisken, Harmke de Groot, Vincent van der Leest, Geert Jan Schrijen, Marten van Hulst, Pim Tuyls
ISCAS6