Convolutional Neural Networks (CNNs) are employed in a broad range of classification tasks. Despite CNNs have reached high accuracy, they have high computational complexity, so employing this method in many applications such as internet of things (IoT) is challenging. To overcome this challenge, CNN hardware accelerators are proposed. As the main activation function employed in the CNNs is ReLU, a large portion of the output becomes zero. Therefore, sparse CNN accelerators are proposed to reduce the computational complexity. Recent studies show that, rather than employing sparse CNN accelerators, it would be ideal to predict the zero outputs and remove the corresponding computations. In this paper, we propose the iMAC accelerator to bypass ineffectual computations (a computation leads to zero). For this purpose, we propose a prediction unit that determines ineffectual computations without accuracy loss. Then we propose a dataflow to bypass ineffectual computations. The results show that by increasing 12% of area and 18% power overhead, iMAC achieves 2.31× speedup and 1.95× energy efficiency without any accuracy loss. With 3% accuracy loss, it further improves the speed and the energy by 2.94× and 2.49×, respectively. Moreover, compared to the previous prediction method, our method achieves higher speedup and improvement.

Fully Homomorphic Encryption (FHE) enables computation directly on encrypted data, and multiple hardware accelerators have emerged. Unfortunately, each accelerator is evaluated using a rigid and proprietary simulator. This makes it challenging to compare accelerators or evaluate the performance impact of individual ideas. Perhaps more importantly, it has proven to be challenging to transfer ideas across accelerators. Each new idea in FHE typically requires changes across the stack, from the security protocol (e.g., KeySwitching), to the memory hierarchy (e.g., on-the-fly key reuse), and individual functional units (e.g., FFT-based polynomial multipliers). Currently, there is no tool for exploring FHE accelerators. We introduce FLASH, an extensible, modular, and opensource simulator for FHE accelerators. We pioneer a new methodology for constructing architecture simulators-compilerlike dialects (or intermediate representations). FLASH includes three distinct yet interoperable dialects for writing imperative code on encrypted types (Security), expressing spatial and temporal data movement of polynomials (PolyDataflow), and creating custom functional units (Modular arithmetic). A transpiler seamlessly ties these dialects, and rapidly high-level-synthesizes (HLS) them to accelerator-specific performance model. Users can implement algorithm-hardware co-design ideas, as transformations of kernels written in our dialects, and do not require time-consuming buggy simulator rewrites. We demonstrate the versatility of FLASH using multiple case studies: i) we conduct the first pubic head-to-head comparison of multiple FHE accelerators. ii) we backport ideas from multiple papers and quantify their impact (e.g., KeySwitching). We can construct an FHE accelerator model from scratch with $\simeq \mathbf{5 0 0}$ lines-of-code (vs. 3000+ when working with existing FHE library and simulator). iii) Finally, we show that we can implement new ideas with modular changes ($\lt50$ lines of code). The dialects helps us affect the changes in a targeted and concise manner.