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Aocheng Qiu

dblp:422/8852 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2025
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 87% Integrated circuit design · 13%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › DRAM › DRAM architecture
3D-stacked DRAM		 0.912025
Scaled 3D-stacked 2T0C DRAM based on indium-tin-oxide transistors with long data retention and fast write speed of 10 ns · Sci. China Inf. Sci. 2025
Memory systems
DRAM		 0.912025
Scaled 3D-stacked 2T0C DRAM based on indium-tin-oxide transistors with long data retention and fast write speed of 10 ns · Sci. China Inf. Sci. 2025
YearPublicationVenuePosition
2025 Scaled 3D-stacked 2T0C DRAM based on indium-tin-oxide transistors with long data retention and fast write speed of 10 ns
Shenwu Zhu, Qianlan Hu, Chengru Gu, Shiwei Yan, Aocheng Qiu, Yanqing Wu
 Sci. China Inf. Sci.5