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SeongJun Yun

dblp:426/0322 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2026
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 77% Hardware accelerators and domain-specific architectures · 23%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › processing-in-memory › computing-in-memory
digital compute-in-memory
1.012026
DH-PIM: Maximizing Computing Unit Utilization in Digital PIM by Dual Half Mode Extension · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026
Memory systems
processing-in-memory
1.012026
DH-PIM: Maximizing Computing Unit Utilization in Digital PIM by Dual Half Mode Extension · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.312026
DH-PIM: Maximizing Computing Unit Utilization in Digital PIM by Dual Half Mode Extension · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026
Hardware accelerators and domain-specific architectures › machine learning accelerator › DNN inference
transformer inference
0.312026
DH-PIM: Maximizing Computing Unit Utilization in Digital PIM by Dual Half Mode Extension · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026

Methods — techniques the papers use, named apart from their topics

pipelined execution · 1.0dual half mode · 1.0
YearPublicationVenuePosition
2026 DH-PIM: Maximizing Computing Unit Utilization in Digital PIM by Dual Half Mode Extension
abstract
Transformer-based Large Language Models (LLMs) rely on both General Matrix-Matrix Multiplication (GEMM) and General Matrix-Vector Multiplication (GEMV) for inference. While existing Processing-in-Memory (PIM) architectures, like HBM-PIM and Newton, efficiently handle GEMV operations, they suffer from low computing unit utilization during GEMM due to frequent input preparation and activation cycles. To address this, we propose Dual Half-mode PIM (DH-PIM), an extension of the Half Division Mode from previous PipePIM. DH-PIM splits sense amplifiers, and computing units into halves, allowing them to execute different operations independently. Dual half mode, which allows both halves of the computing unit to process data broadcast from either half of the sense amplifier, significantly enhances utilization via overlapped and pipelined execution. Our simulations show DH-PIM improves GEMM performance by up to 2.06x in GEMM kernels, with about 1.46x speedup in LLM tasks, compared to HBM-PIM. These performance improvements are achieved with minimal architectural modifications, resulting in low area and energy overhead.
Byoung Jin Kim, Taeyang Jeong, SeongJun Yun, Eui-Young Chung
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3