VLDB 2026 Research / reviewers in the wild / expert
Ouyang Ouyang
dblp:426/1329
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2025
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 67% Embedded and real-time systems · 33% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems
cache |
0.9 | 1 | 2025 | Tight Cache Contention Analysis for WCET Estimation on Multicore Systems · RTSS 2025 |
Memory systems › cache management
cache interference |
0.9 | 1 | 2025 | Tight Cache Contention Analysis for WCET Estimation on Multicore Systems · RTSS 2025 |
Embedded and real-time systems
worst-case execution time analysis |
0.9 | 1 | 2025 | Tight Cache Contention Analysis for WCET Estimation on Multicore Systems · RTSS 2025 |
Methods — techniques the papers use, named apart from their topics
dynamic programming · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Tight Cache Contention Analysis for WCET Estimation on Multicore SystemsabstractWCET (Worst-Case Execution Time) estimation on multicore architecture is particularly challenging mainly due to the complex accesses over cache shared by multiple cores. Existing analysis identifies possible contentions between parallel tasks by leveraging the partial order of the tasks or their program regions. Unfortunately, they overestimate the number of cache misses caused by a remote block access without considering the actual cache state and the number of accesses. This paper reports a new analysis for inter-core cache contention. Based on the order of program regions in a task, we first identify memory references that could be affected if a remote access occurs in a region. Afterwards, a fine-grained contention analysis is constructed that computes the number of cache misses based on the access quantity of local and remote blocks. We demonstrate that the overall inter-core cache interference of a task can be obtained via dynamic programming. Experiments show that compared to existing methods, the proposed analysis reduces inter-core cache interference and WCET estimations by$\mathbf{5 2. 3 1 \%}$and$\mathbf{8. 9 4 \%}$on average, without significantly increasing computation overhead. Shuai Zhao 0004, Jieyu Jiang, Shenlin Cai, Yaowei Liang, Chen Jie, Yinjie Fang, Wei Zhang 0173, Guoquan Zhang, Yaoyao Gu, Ouyang Ouyang, Wanli Chang 0001 |
RTSS | 12 |