VLDB 2026 Research / reviewers in the wild / expert
Shun Katsumi
dblp:426/5447
· DBLP profile ↗
1ranked-venue papers
1as first author
1since 2021 · last 2026
0009-0004-6629-6403ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 46% Integrated circuit design · 23% Parallel and multicore computing · 23% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › high-level synthesis
dynamically scheduled high-level synthesis |
1.0 | 1 | 2026 | EagerlyElastic: Correct-by-Construction Eager Execution in Dynamically-Scheduled HLS · FPGA 2026 |
Parallel and multicore computing
eager execution |
1.0 | 1 | 2026 | EagerlyElastic: Correct-by-Construction Eager Execution in Dynamically-Scheduled HLS · FPGA 2026 |
Integrated circuit design › asynchronous circuit design
elastic circuits |
1.0 | 1 | 2026 | EagerlyElastic: Correct-by-Construction Eager Execution in Dynamically-Scheduled HLS · FPGA 2026 |
Electronic design automation
high-level synthesis |
1.0 | 1 | 2026 | EagerlyElastic: Correct-by-Construction Eager Execution in Dynamically-Scheduled HLS · FPGA 2026 |
Processor architecture and microarchitecture
speculative execution |
0.3 | 1 | 2026 | EagerlyElastic: Correct-by-Construction Eager Execution in Dynamically-Scheduled HLS · FPGA 2026 |
Methods — techniques the papers use, named apart from their topics
formal verification · 1.0circuit rewrite patterns · 1.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | EagerlyElastic: Correct-by-Construction Eager Execution in Dynamically-Scheduled HLSabstractCircuits generated through dynamically-scheduled high-level synthesis (also known as elastic circuits) are highly performant, as circuit execution can adjust at runtime to variable control flow or memory dependencies. While there are many promising opportunities for further optimization, the resulting circuits can be difficult to analyze—the challenge of maintaining circuit correctness forms a major obstacle to the optimization process. Seeking to increase performance, we introduce for the first time eager execution—speculatively executing both sides of a conditional branch in parallel, with results committed based on the branch condition—to elastic circuits. We build on recent work to present eager execution as a set of formally verified circuit rewrite patterns, localized transformations which we prove preserve correctness. This allows us to pursue high performance, while simultaneously guaranteeing that global circuit correctness is maintained at every stage. Our eager execution strongly increases performance using only slight alterations to the control path of the circuit: unlike the prohibitive resource cost of processor eager execution, elastic-circuit eager execution can be effectively enabled without additional computational units. On a set of selected kernels, we achieve an average speed-up of 3.2x, at an average increase of 1.2x in LUTs and 1.3x in FFs, compared to standard elastic circuits. Excitingly, elastic eager execution opens up a new design space of high-performance circuits, generated through correct-by-construction approaches, which we have only just begun to explore. EagerlyElastic is open-sourced under 10.5281/zenodo.17703725. Shun Katsumi, Emmet Murphy, Lana Josipovic |
FPGA | 1 |