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Hansen Idden

dblp:428/6164 · DBLP profile ↗
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2ranked-venue papers
0as first author
2since 2021 · last 2026
0009-0008-1952-4572ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021Databases, data management, data science and information retrieval · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Memory systems · 57% Electronic design automation · 38% Performance modeling and evaluation · 6%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › functional verification
emulation
1.012026
Cylon: Fast and Accurate Full-System Emulation of CXL-SSDs · FAST 2026
Electronic design automation › hardware verification and test › functional verification › emulation
full-system emulation
1.012026
Cylon: Fast and Accurate Full-System Emulation of CXL-SSDs · FAST 2026
Memory systems › virtual memory management
page migration
1.012026
PACT: A Criticality-First Design for Tiered Memory · ASPLOS (2) 2026
Memory systems
page placement
1.012026
PACT: A Criticality-First Design for Tiered Memory · ASPLOS (2) 2026
Memory systems
tiered memory
1.012026
PACT: A Criticality-First Design for Tiered Memory · ASPLOS (2) 2026
Performance modeling and evaluation
workload characterization
0.312026
PACT: A Criticality-First Design for Tiered Memory · ASPLOS (2) 2026

Methods — techniques the papers use, named apart from their topics

hardware performance counters · 1.0analytical modeling · 1.0
YearPublicationVenuePosition
2026 PACT: A Criticality-First Design for Tiered Memory
abstract
Tiered memory systems typically place pages based on access frequency (hotness), yet frequency alone fails to capture the true performance impact. We present PACT, an online, page-granular tiered memory design that elevates performance criticality to a first-class design principle. At its core is Per-page Access Criticality (PAC), a fine-grained metric that quantifies each page's contribution to application performance rather than merely counting accesses. PACT profiles PAC online using a lightweight analytical model that uniquely decomposes per-tier memory-level parallelism via hardware queue occupancy counters, enabling direct CPU stall attribution to individual pages. To handle highly skewed PAC distributions, PACT employs PAC-centric migration policies: eager demotion and adaptive promotion, to dynamically place performance-critical pages in DRAM. Across 13 workloads, PACT achieves up to 61% performance improvement over the best of 7 state-of-the-art tiering designs with up to 50× fewer migrations.
Hamid Hadian, Jinshu Liu, Hanchen Xu, Hansen Idden, Huaicheng Li
ASPLOS (2)4
2026 Cylon: Fast and Accurate Full-System Emulation of CXL-SSDs
Dongha Yoon, Hansen Idden, Jinshu Liu, Berkay Inceisci, Sam H. Noh, Huaicheng Li
FAST2