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Simon Guo 0005

dblp:429/2065 · DBLP profile ↗
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1ranked-venue papers
1as first author
1since 2021 · last 2026
0009-0009-2651-3238ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 100%
Software engineering, system software, and programming languages
1 paper
Program verification · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Program verification
model checking
1.012026
CXLMC: Model Checking CXL Shared Memory Programs · ASPLOS (2) 2026
Memory systems
cache coherence
1.012026
CXLMC: Model Checking CXL Shared Memory Programs · ASPLOS (2) 2026
Memory systems › shared memory
distributed shared memory
0.312026
CXLMC: Model Checking CXL Shared Memory Programs · ASPLOS (2) 2026

Methods — techniques the papers use, named apart from their topics

model checking · 2.0
YearPublicationVenuePosition
2026 CXLMC: Model Checking CXL Shared Memory Programs
abstract
Compute Express Link (CXL) shared memory is an emerging industry standard that will allow for cache coherent sharing of remote memory between many machines. Memory devices will contain large amounts of DRAM that can be shared by many machines in a CXL cluster. This will enable software running on clusters of computers to use shared memory to communicate more efficiently and to share important data between these machines.
Simon Guo 0005, Conan Truong, Brian Demsky
ASPLOS (2)1