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Yossi Khayet

dblp:429/2289 · DBLP profile ↗
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1ranked-venue papers
1as first author
1since 2021 · last 2026
0009-0003-2728-1893ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 91% Performance modeling and evaluation · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › memory consistency
memory consistency model
1.012026
Arm Weak Memory Consistency on Apple Silicon: What Is It Good For? · ASPLOS (2) 2026
Memory systems › memory consistency › memory consistency model
total store order
1.012026
Arm Weak Memory Consistency on Apple Silicon: What Is It Good For? · ASPLOS (2) 2026
Memory systems › memory consistency › memory consistency model
weak memory model
1.012026
Arm Weak Memory Consistency on Apple Silicon: What Is It Good For? · ASPLOS (2) 2026
Performance modeling and evaluation
benchmarking
0.312026
Arm Weak Memory Consistency on Apple Silicon: What Is It Good For? · ASPLOS (2) 2026

Methods — techniques the papers use, named apart from their topics

runtime-configurable TSO · 1.0benchmarking · 1.0
YearPublicationVenuePosition
2026 Arm Weak Memory Consistency on Apple Silicon: What Is It Good For?
abstract
Weak memory models such as the Arm model are perceived as enabling higher performance than strong models such as TSO. We critically test this perception on Apple silicon CPUs, whose runtime-configurable TSO mode enables a direct comparison with native Arm mode. We find that Apple silicon TSO mode preserves Arm weak-memory optimizations, typically yielding execution times within 3% of Arm mode across modern applications and classic benchmarks. Although some applications experience higher TSO slowdowns, we trace these to artifacts of Apple's TSO implementation rather than inherent TSO ordering constraints. Our results challenge the perception that the Arm memory model offers a significant performance advantage over TSO in Apple silicon.
Yossi Khayet, Adam Morrison 0001
ASPLOS (2)1