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Demo Data from VLDB 2026 / reviewers in the wild / expert

Simon Dittrich

dblp:429/2850 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2026
0009-0003-1386-406XORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 62% Electronic design automation · 38%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › cache coherence
cache-coherent interconnect		 1.012026
vCXLGen: Automated Synthesis and Verification of CXL Bridges for Heterogeneous Architectures · ASPLOS (2) 2026
Electronic design automation › hardware verification and test
hardware verification		 1.012026
vCXLGen: Automated Synthesis and Verification of CXL Bridges for Heterogeneous Architectures · ASPLOS (2) 2026
Memory systems
cache coherence		 0.312026
vCXLGen: Automated Synthesis and Verification of CXL Bridges for Heterogeneous Architectures · ASPLOS (2) 2026
Memory systems › memory consistency
memory consistency model		 0.312026
vCXLGen: Automated Synthesis and Verification of CXL Bridges for Heterogeneous Architectures · ASPLOS (2) 2026
YearPublicationVenuePosition
2026 vCXLGen: Automated Synthesis and Verification of CXL Bridges for Heterogeneous Architectures
abstract
Compute Express Link (CXL) offers byte-addressable, cache-coherent remote memory accesses across multiple hosts. Unfortunately, the CXL specification lacks mechanisms to ensure safe interoperability between heterogeneous host architectures with diverse cache coherence (CC) protocols and memory consistency models (MCMs). This semantic gap poses fundamental challenges and a significant barrier to adopting CXL in modern heterogeneous data centers.
Anatole Lefort, Julian Pritzi, Nicolò Carpentieri, David Schall, Simon Dittrich, Soham Chakraborty 0001, Nicolai Oswald, Pramod Bhatotia
 ASPLOS (2)5