In recent years, memristor emulators have been utilized in a wide range of applications including neuromorphic computing, security, analog signal processing, and other related fields. This article introduces a novel electronically tunable dual flux controlled floating memristor emulator employing single Current Controlled Differential Difference Current Conveyor (CCDDCC), a MOS capacitor, and one PMOS transistor. The core of the suggested emulator features an electronically tunable CCDDCC-based feedback circuit. The proposed circuit avoids passive components, diodes, and analog multiplier circuits. The suggested memristor has the ability to tune the area of the pinch hysteresis loop without altering the input frequency, input voltage, MOS capacitance, and active component. The circuit operates effectively within a 300 MHz frequency range and demonstrates a well-defined pinched hysteresis loop. Its performance is evaluated using 180 nm TSMC parameters, with a compact layout area of 758.12 μm². Additionally, the robustness of the circuit is thoroughly assessed through analyses of temperature variations, supply voltage fluctuations, transistor size variations, and process corner simulations.

A half-select disturb-free 11T (HF11T) static random access memory (SRAM) cell with low power, better stability and high speed is presented in this paper. The proposed SRAM cell works well with bit-interleaving design, which enhances soft-error immunity. A comparison of the proposed HF11T cell with other cutting-edge designs such as single-ended HS free 11T (SEHF11T), a shared-pass-gate 11T (SPG11T), data-dependent stack PMOS switching 10T (DSPS10T), a single-ended half-selected robust 12T (HSR12T), and 11T SRAM cells has been made. It exhibits 4.85×/9.19× less read delay ( T RA ) and write delay ( T WA ), respectively as compared to other considered SRAM cells. It achieves 1.07×/1.02× better read and write stability, respectively than the considered SRAM cells. It shows maximum reduction of 1.68×/4.58×/94.72×/9×/145× leakage power, read power, write power consumption, read power delay product (PDP) and write PDP respectively, than the considered SRAM cells. In addition, the proposed HF11T cell achieves 10.14× higher I on / I off ratio than the other compared cells. These improvements come with a trade-off, resulting in 1.13× more T RA compared to SPG11T. The simulation is performed with Cadence Virtuoso 45nm CMOS technology at supply voltage ( V DD ) of 0.6 V.

In this manuscript, a new fractional-order (FO) oscillator is proposed, which employs two fractional-order capacitors (FOC) and two operational trans-conductance amplifiers (OTA). The difference of phase between two output voltages of FO oscillator can be independently controlled. Sensitivity of frequency of oscillations with respect to different circuit parameters is drafted mathematically. The functionality of the proposed structure is confirmed through SPICE simulations with 180nm CMOS technology model parameters and stability of the same is confirmed through pole plot in W-plane using forlocus function of MATLAB. Corner analysis and Monte-Carlo analysis are also carried out to illustrate the robustness of the proposed FO oscillator.

The implementation of the six-transistor (6T) static random access memory cell in deep submicrometer region has become difficult due to the compromise between area, power, and performance, with local and global variations only exacerbating the problem further. To impede the read-write conflict of the 6T cell, the seven-transistor (7T) cell with a noise-margin-free read operation has previously been proposed. But it severely lags in terms of its write ability at lower voltages due to its single-ended write operation. Its single-ended read operation also degrades severely in performance when operating in subthreshold (ST) region. To combat these problems, we propose a 7T cell which operates in the ST region down to 0.4 V with improved dynamic write ability. The novel topology also helps reduce power consumption by achieving a lower data retention voltage point. A read assist has been proposed to greatly enhance the performance of the single-ended read operation in ST region. Large improvements in various performance metrics of the proposed cell have been attained while simultaneously achieving a low area of $0.254~\mu \text{m}^{2}$ per bit cell on the 32-nm technology node.