A logic diagnosis procedure produces a set of can-didate faults that are expected to identify the defects present in a faulty chip. To reduce the number of candidates produced, diagnostic tests are often needed. The use of diagnostic tests increases the storage requirements of a test set. Earlier works reduced the input storage requirements of a fault detection test set by using each stored test to apply several different tests. When applied to diagnostic tests, the tests were selected by performing diagnostic fault simulation of a basic fault model. In this paper, we apply this approach to target large sets of candidate faults produced by a logic diagnosis tool. A procedure for the selection of a subset of the available tests to be used as diagnostic tests is described. Experimental results for simulated defects in benchmark circuits and the logic blocks of an OpenSPARC T1 microprocessor show that the diagnostic test set selected using our approach produces better diagnosis results, with a minimal increase in input storage, compared to a diagnostic test set produced by a commercial tool.

This article describes a defect-oriented test (DOT) approach, which enables a complete physical defect-based automatic test pattern generation (ATPG) for the digital logic area of CMOS-based designs. Total critical area (TCA)-based methods are presented for the generation of needed DOT views to enable the generation of complete DOT-based patterns for detecting all cell-internal and as well all cell-external physical defects. The major aim of these new methods and patterns is to further reduce the defect rate of manufactured ICs, in addition to what is already achieved with traditional and cell-aware test (CAT) fault models. We present test results, including achieved defect rate reduction in defective parts per million (DPPM), from a large 14-nm FinFET design, including a correlation to system-level-test (SLT) fails. For a second, mature 160-nm automotive mixed-signal sensor we present high-volume production test results, again measured in DPPM, and we provide test coverage figures moving away from counting detected faults to calculating detected TCA which is reported as the chip level TCA coverage.

We propose a framework to co-optimize Yield along with Power, Performance and Area (PPA) through the design flow from logic synthesis through placement and routing (APR). We accomplish this by learning from silicon using a combination of test/diagnosis, inline/metrology and Failure Analysis (FA) results to create predictive models using Machine Learning (ML) techniques that are then used during design. Simulation results across three different CPU and Graphics cores show promising results with projected yield improvements of 11-17% with no area and performance / timing penalty with respect to design targets but with tradeoffs to both static and dynamic power. Better joint exploration of the PPA space along with yield indicates it is possible to recover yield with close to iso-PPA with respect to design targets. Pre-silicon results show ~10.4% yield increase with iso-area and -iso-performance and ~1% power penalty on a processor core.

Fail data is collected on a tester to allow defect diagnosis to be carried out. The high volume of fail data that some faulty units produce, and the test application time, motivated the development of procedures for terminating the fail data collection process before it stores the entire fail data for a faulty unit. A procedure for modifying a test set to reduce the fail data volume it produces was developed to complement these approaches, but without considering the constraints of a test data compression method. This article describes a procedure for modifying a stored test set to reduce the fail data volume under a test data compression method where a linear-feedback shift-register is used for on-chip decompression. The constraints of the test data compression method affect the procedure in several important ways. The experimental results for benchmark circuits demonstrate the ability of the procedure to reduce the fail data volume by modifying a stored test set.

As integrated circuit manufacturing advances, the occurrence of systematic defects is expected to be prominent. A methodology for predicting potential systematic defects based on design-for-manufacturability (DFM) guidelines was described earlier. In this paper we first report that, among the faults obtained based on DFM guidelines, there are undetectable faults, and these faults cluster in certain areas of the circuit. Because faults may not perfectly represent potential defect behaviors, defects may be detectable even though the faults that model them are undetectable. Clusters of undetectable faults thus leave areas in the circuit uncovered for potential systematic defects. As the potential defects are systematic, the test escapes can impact the DPPM significantly, and thus lead to circuit malfunction and/or reliability problems after deployment. To address this issue in the context of cell-based design, we propose a logic resynthesis procedure followed by physical design to eliminate large clusters of undetectable faults related to DFM guidelines. The resynthesized circuit maintains design constraints of critical path delay, power consumption and die area. The resynthesis procedure is applied to benchmark circuits and logic blocks of the OpenSPARC T1 microprocessor. Experimental results indicate that both the reduction in the numbers of undetectable faults and the reduction in the sizes of undetectable fault clusters are significant.

Multiple defects are prevalent in early stages of yield improvement for a new technology. When a logic diagnosis procedure is applied to a faulty unit that contains a multiple defect, it sometimes produces a large set of candidate faults. Such a set includes extra candidates that do not match the defect present in the faulty unit. An earlier study indicates that a logic diagnosis procedure may prefer certain faults as candidate faults, causing them to appear as extra candidates in many sets of candidate faults. This points to the possibility of using a small number of observation points to eliminate extra candidates that appear often. This paper takes advantage of this observation to improve the quality of diagnosis by placing observation points. Experimental results for benchmark circuits demonstrate the effectiveness of observation points in reducing large sets of candidate faults.

Design-for-manufacturability (DFM) guidelines are recommended layout design practices intended to capture layout features that are difficult to manufacture correctly. Avoiding such features prevents the occurrence of potential systematic defects. Layout features that result in DFM guideline violations may not be avoided completely due to the design constraints of chip area, performance, and power consumption. A framework for translating DFM guideline violations into potential systematic defects, and faults, was described earlier. In a cell-based design, the translated faults may be internal or external to cells. In this article, we focus on undetectable faults that are external to cells. Using a resynthesis procedure that makes fine changes to the layout while maintaining the design constraints, we target areas of the design where large numbers of external faults related to DFM guideline violations are undetectable. By eliminating the corresponding DFM guideline violations, we ensure that the circuit does not suffer from low-coverage areas that may result in detectable systematic defects escaping detection, but failing the circuit in the field. The layout resynthesis procedure is applied to benchmark circuits and logic blocks of the OpenSPARC T1 microprocessor. Experimental results indicate that the improvement in the coverage of potential systematic defects is significant.

Gate-exhaustive and cell-aware tests are generated based on input patterns of cells in a design. While the tests provide thorough testing of the cells, the interconnects between them are tested only as input and output lines of cells. This paper defines cell-based faults that allow the interconnects to be tested more thoroughly within a uniform framework that only targets input patterns of cells. In contrast to a real cell that is part of the design, a dummy cell is used for defining interconnect-aware faults. Using a gate-level description of the circuit, a dummy cell contains an interconnect, an output gate of the real cell that drives it, and an input gate of the real cell that it drives. Experimental results for benchmark circuits show that many of the interconnect-aware faults are not detected accidentally by gate-exhaustive tests, and that the quality of the test set is improved by targeting interconnect-aware faults. Here, quality is measured by the numbers of detections of single stuck-at faults in a gate-level representation of the circuit.

This paper presents DPPM reduction results achieved with new Defect Oriented Test (DOT) methods/patterns applied to designs manufactured in advanced FinFET technologies. Focus of this paper is on Timing-Aware Cell-Aware Test (TA-CAT) patterns targeting small-delay defects of FinFET transistors, and a new DOT method which explicitly targets chip layout dependent cell-neighborhood defects. Test results from traditional Stuck-at/Transition patterns, from traditional CAT patterns, from TA-CAT patterns, and as well from cell-neighborhood patterns, applied to FinFET technology designs, will be presented in this paper. In addition, a correlation to System-Level-Test fails will be discussed.

A test reordering algorithm is presented to improve the results of scan chain diagnosis when a limited amount of fail data is collected by the tester. Tests are reordered based on information derived by applying an enhanced defect diagnosis procedure to the faulty units with scan defects. Tests that are found important for diagnosis of more faulty units are placed earlier in the test set based on the expectation that these tests will be useful for diagnosis of other faulty units as well. Experimental results collected for benchmark circuits in the presence of single and multiple scan chain defects indicate that reordering tests based on diagnostic information improves the quality of scan chain diagnosis when a limited amount of fail data is collected by the tester.

As part of a yield improvement process, fail data is collected from faulty units. Several approaches exist for reducing the tester time and the volume of fail data that needs to be collected based on the observation that a subset of the fail data is sufficient for accurate defect diagnosis. This article addresses the volume of fail data by considering the test set that is used for collecting fail data. It observes that certain faults from a set of target faults produce significantly larger numbers of faulty output values (and therefore significantly larger volumes of fail data) than other faults under a given test set. Based on this observation, it describes a procedure for modifying the test set to reduce the maximum number of faulty output values that a target fault produces. When defects are considered in a simulation experiment, and a defect diagnosis procedure is applied to the fail data that they produce, two effects are observed: the maximum and average numbers of faulty output values per defect are reduced significantly with the modified test set, and the quality of diagnosis is similar or even improved with the modified test set.

During fail data collection, a tester collects information that is useful for defect diagnosis. If fail data collection can be terminated early, the tester time as well as the volume of fail data will be reduced. Test reordering can enhance the ability to terminate the process early without affecting the quality of diagnosis. In this paper, test reordering targets logic defects based on information that is derived during defect diagnosis. The defect diagnosis procedure is enhanced to identify tests that are useful for defect diagnosis across a sample of faulty instances of a circuit. Tests that are determined to be useful for more faulty instances of a circuit are placed earlier in the test set based on the expectation that the same tests will be useful for other faulty instances of the circuit. The experimental results for logic defects in benchmark circuits support the effectiveness of this approach and indicate that test reordering helps to terminate fail data collection early without impacting the diagnosis quality.

A complete industrial defect diagnosis flow for yield learning includes the use of diagnostic tests. Diagnostic tests improve the ability of a defect diagnosis procedure to provide accurate diagnosis results. Because of the costs involved, diagnostic test generation is carried out only for units where the results of defect diagnosis based on a fault detection test set are not accurate enough. This paper formulates the diagnostic test generation problem under this scenario with the goal of simplifying the test application process for diagnostic tests, taking into consideration that different units require different diagnostic tests. The parameters that the problem formulation targets are the numbers of diagnostic tests for the individual units, and the total number of diagnostic tests for all the units. A lower total number of diagnostic tests increases the similarity between the diagnostic test sets for the individual units. With similar diagnostic test sets, the units are partitioned into groups such that all the units in a group are tested using the same diagnostic test set. The paper describes a diagnostic test generation procedure that uses dynamic test compaction to optimize these parameters.

Faster failure isolation is critical for manufacturing yield ramp and product time to market. Higher diagnosis resolution is essential for faster defect isolation and root-cause identification. A detection oriented test set is targeted for fault coverage and does not provide maximum diagnostic resolution. In this paper, we present the design and architecture of a state of the art diagnostic ATPG tool for industrial-scale designs. We develop a novel diagnostic test generation methodology which first generates deterministic diagnostic test content to distinguish the diagnosis suspects. If tester memory is available then additional N-detect oriented tests are generated to augment the content. Further, we present techniques to improve performance of diagnostic fault simulation for industrial-scale designs. Experimental results on Intel® Core™ microprocessor designs indicate 3X-114X speed up with up-to 2X memory overhead. Silicon failure data collected on sort wafer fails showed the effectiveness of the hybrid diagnostic content in improving the diagnostic resolution by 2.8x to 3X when compared with content generated from an industry standard diagnostic test generator. Silicon results are evaluated on Intel® Core™ microprocessor.

This paper presents an algorithm for reducing the test data volume collected by a tester for defect diagnosis of an IC and the tester time. The tester executes the tests and transfers the failing test responses one by one from the tester capture memory to the tester data-logs. While the tester is transferring the fail data, the proposed algorithm analyzes the failing outputs for every test and determines if the test is a potential contributor to the identification of defects. If not, then the test is eliminated from the tester data-logs. Otherwise, the test may replace an existing test or be added as a new test. The addition and replacement of tests continue until the algorithm determines that the fail data transferred to the tester data-logs is sufficient for accurate defect diagnosis. The early termination of the fail data transfer reduces the overall tester time. The effectiveness of the method was verified using real defects in industry fabricated dies. The algorithm was also implemented in a test program library and integrated into a production fail flow for sort data-log optimization. The overhead of the algorithm was minimal, and yielded a 5x reduction in the test data trasfer time.

With the increasing transistor count and design complexity of modern integrated circuits, a large volume of fail data is collected by the tester for a failing die. This fail data is analyzed by a diagnosis procedure to obtain information about the defects in the die that caused it to fail. However, large portions of the fail data are not necessary for diagnosis. As a result, the diagnosis procedure spends time analyzing unnecessary data, thus decreasing its speed and throughput. We present a methodology to minimize the amount of fail data that is provided to the diagnosis procedure without compromising the diagnosis accuracy (DA). Our methodology evaluates the outputs at which the tests failed to eliminate noncontributing failing tests. The efficacy of our algorithm is demonstrated using fail data from industry fabricated chips. The experimental results show that, on average, our algorithm achieves fail data minimization of 40% while maintaining an average DA of 95%. The speed of the diagnosis procedure is increased by 39%.

This paper describes a method for built-in generation of functional broadside tests for a circuit that is embedded in a larger design, taking functional constraints on its primary input sequences into account. The constraints are captured by functional input sequences of the design. Specifically, the peak switching activity in the circuit under the functional input sequences is used to bound the switching activity during on-chip test generation.

Summary form only given. The major bottleneck for technology scaling is the growing rate of hardware failures. Process variations are becoming extreme and sensitivity to radiation is becoming severe. In addition, intrinsic failures such as device parameter degradation are accelerating the wear-out. All of these are leading to higher random in-filed failures and shorter device lifetime. The 2011 ITRS (International Technology Roadmap for Semiconductors) projects very high bit failure rates of the order of 10-2for SRAM and of 10-3for latches for 16nm high performance technology. Hence, solving reliability challenges for future technologies requires new efficient and cost effective approaches not only to detect and recover from in-filed failures, but also to extend the device lifetime for targeted applications.

Post silicon speed-path debug and production volume diagnosis for yield learning are critical to meet product time to market demand. In this paper, we present Logic BIST speed-path debug technique and methodology for achieving higher frequency demand. We have developed a methodology for Logic BIST production fail volume diagnosis and presented tester time and memory overhead tradeoffs and optimization for enabling volume diagnosis. Results are presented showing successful isolation of silicon speed-paths on Intel® SOCs.

Following design-for-manufacturability (DFM) guidelines during chip design can lower the possibility of occurrence of systematic defects. In this paper, we investigate the use of DFM guidelines during the defect diagnosis process with the goal of identifying which DFM guidelines are responsible for the defects present in failing chips. We also introduce a new metric called diagnostic coefficient that allows us to rank the guidelines according to their contribution of hard-to-diagnose defects. DFM guidelines that are ranked high should be applied during chip design in order to obtain chips that are easier to diagnose.

Diagnosis of functional failures can be used to debug design issues, isolate manufacturing defects, and improve manufacturing yield. Automated failure analysis and rapid root-cause isolation is critical for meeting ever decreasing product time to market demand. Conventional debug approach requires in-depth architecture knowledge and debug expertise. In this paper, we present a two phase approach for isolating microprocessor functional failures. First, failing functional blocks are identified utilizing functional fault simulation. Then, algorithmic diagnosis techniques are applied to accurately identify the failing signals within a functional block. Results are presented showing successful isolation of silicon defects on Intel® Core¿dual-core processor.

Debug of at-speed failures using functional tests is a key challenge as part of frequency pushes during post-silicon debug to improve performance of high performance designs, especially microprocessors. In this paper, we present a technique to automate the debug of speed path failures using failing functional tests by extracting information from design-for-debug features and then algorithmically isolating the internal speed-paths that could be the source of the failures. Results from application of the technique during silicon debug on the Intel ® Core ™ i7 quad-core processor is presented.

A methodology using design-for-manufacturability (DFM) layout guidelines as a basis for modeling and detecting systematic defects was proposed earlier. In this paper, we show that this methodology can be extended to prioritize layout locations according to the importance of applying DFM guidelines to them. Prioritization is done based on test considerations including coverage and test set size. In particular, this methodology can identify layout locations where failure to follow a DFM guideline may result in test holes due to hard-to-detect defects. The prioritized list can be used by layout tools to create circuits that are easier to test.

In this paper we present a fault diagnosis procedure for defects in the scan clock tree. We first identify the candidate clock tree buffers common to failing chains by backtracing. We then evaluate and rank these candidates by forward tracing and simulation. Experimental results show that the proposed procedure provides accurate diagnosis of scan clock failures.

With shrinking feature sizes of manufacturing processes, the occurrence of systematic defects is expected to increase. In this paper, we present techniques for identifying potential systematic defect candidates from design-for-manufacturing (DFM) layout guidelines. DFM guidelines are tightened to find layout locations as potential sites for systematic defects, affected transistors are identified at the schematic level, and defect behaviors are translated to gate level logic faults. Experimental results are presented on an Intel Pentiumê4 design for the evaluation of existing tests in screening systematic failures and identifying potential test holes. Additional test content is generated for improving test quality.

In this paper, we identify two main bottlenecks in the functional diagnosis flow and propose new ways to overcome these. Our approach completely eliminates the "primary input (PI) pattern generation and simulation" step and instead employs scan-dump values extracted from the tester. We utilize backward and forward logic implications of the scan-dump values to reconstruct more logic values for the circuit signals. Furthermore, we employ the reset state for the non-scan latches of the design to increase the number of specified signals in the overall circuit. Experimental results on stuck-at faults on industrial designs show that, in most cases, these reconstructed values are sufficient to correctly diagnose a fault, thereby avoiding hours of conventional functional diagnosis runtimes.

Diagnostic fault simulation is used to determine the pairs of faults distinguished by a given test set or test sequence. Diagnostic test generation is used to generate tests that distinguish pairs of faults. Typically, the test sets or test sequences contain tests that detect all the detectable target faults. In this paper, a framework for diagnostic fault simulation and test generation is described, based on structural circuit characteristics called z-sets. These characteristics are used to show that certain fault pairs are guaranteed to be distinguished by a fault detection test set. Such fault pairs do not need to be considered during diagnostic fault simulation or test generation that starts from a fault detection test set. Experimental results for single stuck-at faults in full-scan benchmark circuits demonstrate that only small percentages of fault pairs need to be considered during diagnostic fault simulation or test generation once a fault detection test set is available. The concept of -sets is extended to define z-detections. This concept uses the results of conventional fault simulation to determine additional fault pairs that are guaranteed to be distinguished by a fault detection test set. The concept of z-sets is also extended to define difference-sets (or d-sets) that provide even fewer targets for diagnostic test generation.

For nanometer manufacturing fabrication process, it is critical to narrow down the defect location for successful physical failure analysis. This paper presents a mixed-level diagnosis technique, which first performs diagnosis at logic level, and then performs switch-level analysis to locate a defect at transistor level. An efficient single pass mixed-mode diagnosis flow proposed to isolate defects within a cell. Experimental results showed significant improvement in precision over traditional logic diagnosis with only a fractional increase in run-time. The proposed mixed-level diagnosis technique was applied to successfully isolate silicon defects

Production test data from more than 500,000 chips is analyzed to understand the correlation between the number of defective chips detected by a set of test patterns and the coverage values of these test patterns with respect to various test metrics. Experimental results show that the gate exhaustive metric has the highest correlation when compared to the stuck-at and the bridge coverage estimate metrics, especially for high coverage test patterns. More than 69% of all test patterns can be removed from the test set without reducing the number of detected chips - more than 99% of these patterns are required to obtain high stuck-at coverage. None of the test metrics are very effective in predicting which subset of a given set of test patterns can be removed from the test set without compromising test quality before the patterns are actually applied to manufactured ICs

A procedure for using fault dominance in a large volume diagnosis environment is described. Fault dominance is shown to be useful for reducing the fault simulation time during diagnosis when used together with the concept of pattern dependence and maximally dominating faults. Results for both ISCAS benchmarks and industrial circuits are reported. The results show 9 % to 44% average reduction in the fault simulation time for these circuits

We propose techniques to speed up diagnostic fault simulation for circuits without full-scan which may need multi-cycle tests. First, we introduce the concept of z-sets for circuits without full scan and show how z-sets can be used in a preprocessing step to improve the performance of diagnostic fault simulation. Further, an implementation of an equivalence identification tool that executes concurrently with diagnostic fault simulation is described along with methods to increase its efficiency by prioritizing fault pair selection and reducing interprocess communication. Finally, a combination of both these techniques is analyzed and the performance benefit is presented. Experimental results on ISCAS'89 benchmarks and industrial circuits indicate that diagnostic fault simulation is substantially faster by 20.6 to 46.9% when z-sets are used along with concurrent equivalent fault identification

This paper presents an algorithmic scan-chain-fault diagnosis procedure. The diagnosis for a single scan-chain fault is performed in three steps. The first step uses special chain test patterns to determine both the faulty chain and the fault type in the faulty chain. The second step uses a novel procedure to identify the suspect scan cell within a range of scan cells. The final step further improves the diagnostic resolution by ranking the suspect scan cells inside this range. The proposed technique handles both stuck-at and timing failures (transition faults and hold-time faults). The application of the procedure in a production test flow is discussed. Simulation and silicon results from several products show the effectiveness of the proposed method.

In the design cycle of high-performance integrated circuits, it is common that certain components are designed directly at the transistor level. This level of design representation may not be appropriate for test generation tools that usually require a model expressed at the gate level. Logic extraction is a key step in test model generation to produce a gate-level netlist from the transistor-level representation. This is a semi-automated process which is error-prone. Once a test model is found to be erroneous, manual debugging is required, which is a resource-intensive and time-consuming process. This paper presents an in-depth analysis of typical sets of extraction errors found in the test model representations of the pipelines in high-performance designs today. It also develops an automated debugging solution for single extraction errors for pipelines with no state equivalence information. A suite of experiments on circuits with similar architecture to that found in the industry confirms the fitness and practicality of the solution.

Test model generation is common in the design cycle of custom made high performance low power designs targeted for high volume production. Logic extraction is a key step in test model generation to produce a logic level netlist from the transistor level representation. This is a semi-automated process which is error prone. The paper analyzes typical extraction errors applicable to clocking schemes seen in high-performance designs today. An automated debugging solution for these errors in designs with no state equivalence information is also presented. A suite of experiments on circuits with similar architectures to those found in the industry confirm the fitness and practicality of the solution.

X-compactor is an X-tolerant test response compactor that is useful for massive reduction of test data volume and test time. This paper presents a technique for identifying failing flip-flops during scan test directly from the compacted response obtained from X-compactor outputs. The identified failing flip-flops can be used for several purposes - as inputs to a scan-based diagnosis tool to diagnose defects in combinational logic, to identify defective scan chains, or for statistical data collection during high volume manufacturing to analyze deformations and yield limiters. The presented technique requires no modification to existing scan-based diagnosis tools and has been used in high volume manufacturing flows. The experimental data from production test flows demonstrates its effectiveness for industrial designs.

Given the trends in manufacturing process, design and their interaction can diagnosis play a greater and more central role in achieving higher yields? Can automated logic diagnosis solutions become a fundamental driver of yield improvement or will it just remain a secondary endeavor?

We define the concepts of z-sets and z-detections for combinational circuits (or the combinational logic of scan circuits). Based on these concepts we define structural characteristics and characteristics based on fault simulation. We show that these characteristics determine the numbers of fault pairs that are guaranteed to be distinguished by a given fault detection test set. These fault pairs do not need to be considered during diagnostic fault simulation or test generation. We demonstrate that benchmark circuits as well as industrial circuits have these characteristics to a larger extent than may be expected. As a result, only small percentages of fault pairs need to be considered during diagnostic fault simulation or test generation once a fault detection test set is available. In addition, these fault pairs can be identified efficiently.

This paper evaluates N-detect scan ATPG patterns for their impact to test quality through simulation and fallout from production on a Pentium 4 processor using 90 nm manufacturing technology. An incremental ATPG flow is used to generate N-detect test patterns. The generated patterns were applied in production with flows to determine overlap in fallout to different tests. The generated N-detect test patterns are then evaluated based on different metrics. The metrics include signal states, bridge fault coverage, stuck-at fault coverage and fault detection profile. The correlation between the different metrics is studied. Data from production fallout shows the effectiveness of N-detect tests. Further, the correlation between fallout data and the different metrics is analyzed.

We address the problem of design-for-diagnosability, i.e., improving the accuracy of fault diagnosis or reducing its complexity through the insertion of observation points. To perform design-for-diagnosability efficiently, we use a procedure developed earlier for computing the number of fault pairs, N/sub P/, that are not guaranteed to be distinguished by a given test set. By using the concept of z -detection, N/sub P/ can be computed efficiently without enumerating fault pairs and without performing non-fault dropping fault simulation. We study the possibility of increasing the diagnosability of a circuit by inserting observation points so as to reduce N/sub P/. Our results include the following. (1) We find experimentally the number of observation points that need to be inserted in order to achieve a close-to-minimum value for N/sub P/. (2) We describe an efficient procedure for inserting a given number of observation points so as to reduce N/sub P/. We present experimental results for benchmark circuits to demonstrate the accuracy of using N/sub P/ to guide a design-for-diagnosability process.

The process of root-causing failures is necessary and critical for ICs given both aggressive designs and new manufacturing processes. Economic considerations makes the whole root-causing process better, faster and cheaper. Progress requires development not just on individual tools but on the whole global process.

Generation of ATPG patterns require a gate-level simulation model and associated constraints. If the models and the related constraints used to generate patterns are erroneous, then the patterns will likely fail on silicon. The process of debugging pattern failures on silicon using manual reason in the absence of automated techniques is very time consuming. Further, techniques used for automated defect diagnosis cannot be directly applied to this problem. In this paper we present techniques for debugging ATPG patterns failing on silicon. An automated tool that implements these techniques and is capable of debugging most common errors found in ATPG models and constraints is presented. Results from applying the capability on Intel Pentium-4 processor's ATPG patterns are presented.

This paper studies the impact of N-detect scan ATPG patterns on test quality and associated test costs. An incremental method for test generation is presented. Metrics to evaluate the richness of the test set are presented. The natural N-detect profiles of regular one-detect test sets and the impact to test data volume and test time of generating additional patterns is studied. Results are presented on an lntel/spl reg/ Pentium/spl reg/ 4 processor. Simulation results from evaluating the patterns on layout extracted and random bridges are presented. Silicon data from production test shows the effectiveness of N-detect tests.

Effective generation of diagnostic vectors can be assisted by a fast diagnostic fault simulator and an equivalence identification tool. Diagnostic fault simulation can be an expensive process for large circuits. If a large number of fault pairs are passed to an equivalence identification tool, it would take a long time. In this paper, a novel approach is proposed to concurrently execute diagnostic fault simulation and equivalence identification during diagnostic test generation, thereby reducing the overall execution time. Experimental results on industrial circuits and benchmark circuits demonstrate the potential of the proposed method.

In this paper, we present a scan chain fault diagnosis procedure. The diagnosis for a single scan chain fault is performed in three steps. The first step uses special chain test patterns to determine both the faulty chain and the fault type in the faulty chain. The second step uses a novel procedure to generate special test patterns to identify the suspect scan cell within a range of scan cells. Unlike previously proposed methods that restrict the location of the faulty scan cell only from the scan chain output side, our method restricts the location of the faulty scan cell from both the scan chain output side and the scan chain input side. Hence the number of suspect scan cells is reduced significantly in this step. The final step further improves the diagnostic resolution by ranking the suspect scan cells inside this range. The proposed technique handles both stuck-at and timing failures (transition faults and hold time faults). The extension of the procedure to diagnose multiple faults is discussed. The experimental results show the effectiveness of the proposed method.

Recent techniques for path delay fault diagnosis have addressed the problem in combinational circuits and sequential circuits. The root cause of a path delay fault test failure is narrowed down to a set of functionally sensitized paths and this set is further reduced by post processing the set of passing tests. In this paper, we present a method for narrowing down the suspects further to a set of segments on the failing functionally sensitized paths. The proposed method is implemented and applied to a set of industrial circuits and it is found to be very effective in determining the defective segments that explain excessive delays along paths.

This article describes a diagnostic fault simulator for stuck-at faults in sequential circuits that is both time and space efficient. The simulator represents indistinguishable classes of faults as memory efficient lists. The use of lists reduces the number of output response comparisons between faults and hence speeds up the simulation process. The lists also make it easy to drop faults when they are fully distinguished from other faults. Experimental results on the ISCAS89 circuits show that the simulator runs significantly faster than an earlier work based on distinguishability matrices, and for large circuits is faster and more memory efficient than a recent method based on lists of indistinguishable faults. The paper provides the first reports on pessimistic and optimistic diagnostic measures for all faults of the large ISCAS circuits with known deterministic tests. The diagnostic fault simulator has also been modified to diagnose defects, given the output responses of failing devices. Results on simulated bridging defects show that the diagnosis time is comparable to the time for fault simulation with fault dropping.

Logic fault diagnosis or fault isolation is the process of analyzing the failing logic portions of an integrated circuit to isolate the cause of failure. Fault diagnosis plays an important role in multiple applications at different stages of design and manufacturing. A logic diagnosis tool with applicability to a spectrum of logic DFT, ATPG and test strategies including full/almost fullscan circuits with combinational ATPG, partial-scan and non-scan circuits with sequential ATPG and to functional patterns in general is presented. Novel features incorporated into the tool include static and dynamic structural processing for partial-scan circuits, windowed fault simulation, and diagnostic models for open defects and cover algorithms for multiple fault diagnosis. Experimental results include simulation results on processor functional blocks and silicon results on chipsets and processors from artificially induced defects and production fallout.

A technique to perform logic diagnosis of defects that cause interconnects in a digital logic circuit to become open or highly resistive is presented. The novel features of this work include a diagnostic fault model to capture potential faulty behaviors in the presence of an open defect and diagnosis algorithms that leverage the diagnostic model while circumventing the need for detailed circuit-level (SPICE) simulation and extraction of parasitic capacitance. Other aspects of the technique include a path-tracing procedure to limit the number of interconnects that need to be analyzed and extensions for multiple defects. Experimental results include simulation results on processor functional blocks and silicon results on a chipset from artificially induced defects and production fallout.

With the increase in the complexity of VLSI circuit design, logic design errors can occur during synthesis. In this work, we present a method for multiple design error diagnosis and correction. Our approach uses the results of test vector simulation for both error detection and error correction. This makes it applicable to circuits with no global BDD representation. In addition, diagnosis is performed through an implicit enumeration of potentially erroneous lines in an effort to avoid the exponential explosion of the error space. Experimental results on ISCAS'85 benchmark circuits show that our approach can typically detect and correct 1, 2 and 3 errors within seconds of CPU time.

A deductive technique is presented that uses voltage testing for the diagnosis of single bridging faults between two gate input or output lines and is applicable to combinational or full-scan sequential circuits. For defects in this class of faults the method is accurate by construction while making no assumptions about the logic-level wired-AND/OR behaviour. A path-trace procedure starting from failing outputs deduces potential lines associated with the bridge. The information obtained from the path-trace from failing outputs is combined using an intersection graph to make further deductions. All candidate faults are implicitly represented, thereby obviating the need to enumerate faults and hence allowing the exploration of the space of all faults. Results are provided for all large ISCAS89 benchmark circuits.

A diagnosis technique that integrates the storage of precomputed information with some dynamic computation for the diagnosis of bridging faults in synchronous sequential circuits with no-scan or partial-scan is presented. The method addresses the accuracy, storage requirements, and computational complexity required for diagnosis. A combination of adaptively simulating the behavior of a bridging fault and storing faulty state information at select vectors ensures accuracy with low storage requirements. The combination of adaptive simulation, state storage, and pathtracing has low computational requirements. Experimental results are provided for the ISCAS89 benchmark circuits.

State information of a sequential circuit can be used to evaluate the complexity of test generation.The ratio of valid states to all the states of the circuit is an important indicator of test generation complexity.Using valid states obtained via logic simulation, a testability measure based on the density of encoding is proposed for scan flip flop selection.A second testability measure based on the test generation state information is also presented and used to select scan flip flops.Cycles are broken selectively on the basis of the circuit state information.Good fault coverage and test efficiency are obtained when fewer scan flip flops than the minimum cut set are selected.Experimental results are presented to demonstrate the effectiveness of the method.

A dynamic diagnosis scheme for synchronous sequential circuits is proposed. In contrast with schemes like fault dictionaries no prior computation and storage of fault symptoms is performed. The technique combines cause-effect and effect-cause strategies. Cause-effect analysis is performed by single stuck at fault simulation followed by a matching algorithm. Effect-cause analysis is performed by an error propagation back-trace starting from the falling outputs. The error propagation back-trace eliminates from consideration faults that could not have caused the failing symptoms. The procedure is exact for defects behaving as single stuck-at faults. Experimental results are provided for the ISCAS89 benchmark circuits.

This paper describes a diagnostic fault simulator for stuck-at faults in sequential circuits that is both time and space efficient. The simulator represents indistinguishable classes of faults as memory efficient lists. The use of lists reduces the number of output response comparisons between faults and hence speeds up the simulation process. The lists also make it easy to drop faults when they are fully distinguished from other faults. Experimental results on the ISCAS89 circuits show that the simulator runs significantly faster than an earlier work based on distinguishability matrices and is faster and more memory efficient than a recent method based on lists of indistinguishable faults. The paper provides the first reports on pessimistic and optimistic diagnostic measures for all faults of the large ISCAS circuits. 1 Introduction The aim of fault location or diagnosis is to locate device failures. Diagnosis may be intended for identification and replacement of a faulty sub-circui...

We propose a new scheme for built-in test (BIT) that uses multiple-polynomial linear feedback shift registers (MP-LFSR's). The same MP-LFSR that generates random patterns to cover easy to test faults is loaded with seeds to generate deterministic vectors for difficult to test faults. The seeds are obtained by solving systems of linear equations involving the seed variables for the positions where the test cubes have specified values. We demonstrate that MP-LFSR's produce sequences with significantly reduced probability of linear dependence compared to single polynomial LFSR's. We present a general method to determine the probability of encoding as a function of the number of specified bits in the test cube, the length of the LFSR and the number of polynomials. Theoretical analysis and experiments show that the probability of encoding a test cube with s specified bits in an s-stage LFSR with 16 polynomials is 1-10/sup -6/. We then present the new BIT scheme that allows for an efficient encoding of the entire test set. Here the seeds are grouped according to the polynomial they use and an implicit polynomial identification reduces the number of extra bits per seed to one bit. The paper also shows methods of processing the entire test set consisting of test cubes with varied number of specified bits. Experimental results show the tradeoffs between test data storage and test application time while maintaining complete fault coverage.>