Cardiovascular diseases remain a leading global health threat, with arrhythmia being a key early indicator of cardiac abnormalities. The need for continuous cardiac monitoring has driven demand for portable, low-power arrhythmia detection systems. This paper presents a low-power mixed-precision System-on-Chip (SoC) solution designed for arrhythmia detection using 12-lead electrocardiogram (ECG) signals. The proposed approach employs a dynamically reconfigurable convolutional neural network (CNN) architecture with flexible hyperparameters, enhancing hardware adaptability while reducing resource overhead and power consumption. At the computation level, an 8-bit and 16-bit mixed-precision floating-point multiplier is introduced to effectively balance arithmetic accuracy and energy efficiency. Furthermore, clock gating and multi-threshold voltage techniques are employed at the digital back-end to further reduce the power consumption of the chip. Through system-level and module-level optimization, the proposed chip design is of great significance for enabling low-power arrhythmia detection in power-constrained portable medical devices.

Device authentication protocols based on a strong physical unclonable function (PUF) show promise for enhancing Internet of Things security. However, a strong PUF is vulnerable to machine learning (ML) attacks. This paper proposes a Feistel structure sequential obfuscation-based PUF (Feistel-PUF) to resist ML attacks. When the PUF is obfuscated by the Feistel structure, the challenge-response relationship resembles that of sequential logic circuits. Specifically, each response depends on both current and historical challenges, thereby significantly increasing the complexity of the challenge-response mapping. Experimental results showed that even with 1 million collected challenge response pairs, the prediction accuracies of ML attacks on Feistel-PUF remained at approximately 50%. Notably, the obfuscation process excluded response data, thereby preserving the randomness, reliability, and uniqueness of PUF with negligible performance degradation. The Feistel structure was iteratively reused for sequential obfuscation processing, maintaining constant and minimal hardware overhead. We propose a novel approach that combines the Feistel-PUF with an authentication protocol. This system synchronizes obfuscation parameters during the initial registration phase and implements dynamic updates throughout the authentication process. This approach allows the obfuscation structure to be made public, thereby overcoming the reliance on structure or algorithm secrecy in traditional dynamic challenge obfuscation schemes. The security of the protocol was confirmed by subjecting it to ProVerif verification and security analysis.

Addressing security threats faced by high efficiency video coding (HEVC) video devices in open deployment environments, this article proposes a HEVC Transform and Quantization (TQ)-based Software Physical Unclonable Function (TQ-SPUF). By overclocking the HEVC TQ module, this function induces clock violations on the critical path, thereby generating a stable and unique device fingerprint. Meanwhile, a two-stage postprocessing scheme combining majority voting and butterfly-xoroperations is employed to generate stable and uniform device fingerprints. Based on the proposed TQ-SPUF, a lightweight challenge-response authentication protocol was designed to achieve device identity binding. Furthermore, the PUF-gated session key is utilized to drive a dual-perturbation selective encryption scheme, which introduces both fixed- and random-position perturbations into the I-frame network abstraction layer units. In this way, semantic information exploitable was effectively disrupted, thereby preventing content recovery or tampering. Experimental results show that the proposed TQ-SPUF achieves 98.84% randomness and 49.15% uniqueness, passing part of the NIST test. Moreover, the encrypted videos exhibit an average peak signal-to-noise ratio (PSNR) of 10.4313dB and an average structural similarity index measure (SSIM) of 0.2935. This indicates that the encrypted content is visually incomprehensible, thereby achieving video anti-tampering protection.

In the era of intelligent computing, with the aid of Internet of Things (IoT) technology, artificial intelligence (AI) chips can be embedded at the terminal, object, edge, and cloud levels, ultimately achieving the vision where there is computation, there is AI intelligence. This not only enhances the efficiency of production and daily life but also exponentially increases the risk of privacy information leakage within AI models. This article leverages the characteristics of strong physical unclonable functions (PUFs), in which the inherent feature information is hidden in physical variations and difficult to steal, to design a security protocol based on strong PUFs that provides effective protection for AI model parameters in the IoT environment. The protocol treats AI model parameters as responses and selects challenges capable of generating these responses. Since the responses generated by the challenges can be considered as randomly generated, transmitting the challenges does not disclose the response information, thus avoiding the risk of parameter hacking. Additionally, the protocol utilizes machine-learning modeling techniques and lightweight encryption technologies to reduce the storage costs for identity information and the computational overhead of encryption operations. Through a security analysis of the protocol, it demonstrates that even under ideal attack conditions, the proposed protocol can resist various attacks. By using formal verification with the ProVerif tool, it confirms the security of the protocol flow and the effective protection of private information.

With the increasing number of devices in the Internet of Things (IoT), security has become a necessary feature. Compared to traditional key encryption methods, IoT device authentication protocols based on strong Physically unclonable function (PUF) have the advantage of being difficult to leak and tamper with. In addition, the protocol can enhance the resistance of strong PUFs to machine learning (ML) attacks by encrypting private information. However, the quality of the authentication is strongly related to the stability of the generated responses. If a large cost is incurred to improve the stability of the strong PUF, it will consume the already scarce resources of the device. This article proposes a challenge screening strategy to improve the response stability of a commonly used strong PUF, arbiter PUF (APUF). First, a precise modeling method of APUF is carried out using the logistic-regression ML algorithm. Subsequently, random noise is injected into the challenges or PUF mathematical model and then calculated to estimate whether a stable response can be produced. Finally, stable challenges are used for IoT device authentication, while the threshold of the protocol is increased in parallel. Experimental verification shows that the proposed strategy can increase the stability of APUF responses to 100% at different temperatures. Furthermore, it does not consume hardware overhead at the device end, which is of particular significance for applications in resource-constrained conditions.

Unmanned Aerial Vehicle (UAV) swarms networks have gained increasing significance in daily life and work. However, current UAV authentication protocols face critical security challenges such as high computational overhead, complex key management, and vulnerabilities to network attacks. This paper proposes a hierarchical authentication protocol that enhances resilience against attacks while maintaining ultra-low overhead. The protocol employs a two-tier mutual authentication architecture, comprising authentication between the base station and the server, and between the server and the UAV leader. This design effectively reduces the risk of single-point failure and improves scalability in large-scale swarm scenarios. Physical unclonable function (PUF) technology establishes secure UAV identities, combined with randomized leader election enhance security, reduce overhead, and increase attacker localization complexity. This paper presents a lightweight cryptographic strategy that combines hash-based challenge encryption and XOR-based response obfuscation to disrupt predictable PUF challenge-response mappings, countering machine learning (ML)-based modeling attacks. The proposed protocol passes security tests using ProVerif and Scyther. The scheme achieves 58.21% lower communication costs than existing approaches, with an authentication overhead of 58.04 μs.

Physically unclonable functions (PUFs) have significant potential in the field of information security applications. To reduce the area of PUF cells and improve the utilization of the PUF entropy source, a dynamic division multiplexing bistable PUF with independent output response is proposed. Initially, a bistable PUF model is constructed by dividing traditional cross-coupled bistable PUF cells. The pull-up (pull-down) network employs large transistor sizes to minimize process variations, while the pull-down (pull-up) network, as the main PUF entropy source, utilizes the minimum transistor size to maximize random process variations. Subsequently, a cross-coupled twin cell with a symmetrical structure and shared word lines is designed, and a PUF cell array is composed ofntwin cells. Finally, the PUF cell array is dynamically configured using the output signal from a decoder. In this configuration, a single selected cell (with large deviation) and$n-1$unselected cells connected in parallel (with negligible deviation) collectively form a bistable PUF circuit for dynamic division multiplexing. The proposed PUF can operate in two independent modes, each of which can generate a 2304-bit feature key. The design is fully customized using the Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm process, and the area (feature size) of a twin cell is only$1.32~\mu $m2(308 F2). Chip test results demonstrated that the proposed PUF achieved the entropy of 0.9999 (0.9997), the uniqueness of 49.9% (49.7%), and the reliability of 99.1% (97.7%) in the Ncell PUF (NC-PUF) [Pcell PUF (PC-PUF)] mode, respectively.

The novel nonvolatile computing-in-memory (nvCIM) technology enables data to be stored and processed in situ, providing a feasible solution for the widespread deployment of machine learning algorithms in edge AI devices. However, current nvCIM approaches based on weighted current summation face challenges such as device nonidealities and substantial time, storage, and energy overheads when handling high-precision analog signals. To address these issues, we propose a resistive random access memory (RRAM)-based binary convolution macro for constructing a complete binary convolutional neural network (BCNN) hardware circuit, accelerating edge AI applications with low-weight precision. This macro performs error compensation at the circuit level and provides stable rail-to-rail output, eliminating the need for any ADCs or processor to perform auxiliary computations. Experimental results demonstrate that the proposed BCNN full-hardware computing system achieves on-chip recognition accuracy of 90.7% (98.64%) on the CIFAR10 (MNIST) dataset, which represents a decrease of 0.98% (0.59%) compared to software recognition accuracy. In addition, this binary convolution macro achieves a maximum throughput of 320 GOPS and a peak energy efficiency of 578 TOPS/W at 136 MHz.

Security and cost efficiency are of utmost importance for embedded processors when it comes to limiting hardware resources in IoT applications. This brief presents a security reduced instruction set computer-five (RISC-V) specific instruction set extension (ISE) designed based on hardware-assisted orthogonal obfuscation for hardware security. The orthogonal obfuscation defines an architecture geared toward high-security processors that supports a Pay-Per-ISE function using a key management unit (KMU), thus capable of supporting the customization of the key for a user’s partially authorized ISE and controlling the unlocking of the specific ISE. The proposed security RISC-V test chip is fabricated in a 65-nm CMOS technology with a core area occupying about 0.739 mm2. The measured results demonstrate that our processor realizes the instruction set authorization function. The results show an average power of 52.8 mW at 1.2 V, a hardware overhead of <3% at 50 MHz, and a 30% improvement in security.

Hardware Trojans are malicious design modifications, which pose severe threats to hardware security and trust. Since integrated circuit (IC) designs are difficult to modify after chip fabrication, it is of great importance to detect Trojans in the early design stage. In this work, we propose a novel hardware Trojan detection method at register transfer level (RTL) through semantic feature extraction and natural language processing (NLP). We convert the hardware design to control and data flow graph (CDFG) and develop a depth-first search and sliding window based algorithm for extracting and segmenting paths. This process preserves the structural and semantic features of RTL code. We then employ the NLP technique to perform Trojan detection at the granularity of RTL code statement. Specifically, we train the FastText model, which is proficient in word representation and text classification, to precisely pinpoint the Trojan-infected statements. We further integrate the word bigram features during the training process to improve the Trojan detection performance. Experimental evaluations using Trust-Hub benchmarks show that the proposed method can successfully pinpoint hardware Trojans with true positive rate (TPR), true negative rate (TNR), accuracy and F1-score of 97.77%, 99.95%, 98.86% and 97.46% respectively on average.

With the development of Internet of Things technology, there is an increasing demand for security protection under extreme resource-constrained conditions. Hardware-based physical unclonable functions (PUFs) become less effective as they require hardware replacement. In this paper, a design scheme of timing-violation-soft PUF (TVS PUF) based on carry-lookahead adder (CLA) is proposed for resource-constrained systems, by studying the metastable characteristics of flip-flop under timing violation status and the transmission path delay deviation of arithmetic operation circuits. Firstly, a synchronous timing module (STM) composed of a 32-bit CLA and flip-flops is constructed using Xilinx Artix-7 FPGA. Then, timing violation are induced in the STM by increasing the clock frequency using a Mixed-Mode Clock Manager (MMCM). Finally, by comparing the output values of the STM under timing violation status with those under normal operation status, the parity of flipped bits is used as the judgment criterion for PUF response, establishing the mapping relationship between challenges and responses. Experimental results demonstrate that the proposed PUF can utilize the existing hardware structure to generate 264challenge-response pairs (CRPs), exhibiting good randomness (passing 12 NIST test items), uniqueness (49.93%), and reliability (97.39%). When collecting up to 106groups of CRPs, the attack prediction rates of four common machine learning algorithms remain close to the 50% baseline of random guessing.

The Internet of Things (IoT) plays an important role in all aspects of production and day-to-day life. However, owing to the frequently trusted authentication vulnerabilities, the physical unclonable function (PUF) has unique advantages in the field of equipment authentication because of its nonstorage and nonvolatility. Nevertheless, PUFs are vulnerable to machine learning (ML) attacks. Once a model is constructed accurately, the secrecy of the PUF is lost. Therefore, Bagua matrices are proposed in this study, which can greatly reduce the accuracy of modeling by encrypting the challenge information. On this basis, a whole-process configurable IoT sensing device protocol was constructed for authentication and transmission, and different matrix encryption methods were configured according to the needs of the different devices. Moreover, on the premise of trusted authentication, the perceptual information can be encrypted using a preset matrix. According to the implementation results of the scheme, the resistance to the ML attacks of the PUF improved significantly and the device authentication and encrypted transmission could operate normally.

High-precision miniaturized micromechanical accelerometers are used extensively in the civilian and military fields. A novel self-test-on-chip method and time-multiplexing feedback method for capacitive accelerometers were proposed in this work. The self-test-on-chip circuit can simulate an acceleration signal to test the harmonic distortion without a high-precision shaker table. Using digital timing control, the time-multiplexing feedback can reduce the coupling between the feedback signal and the detection signal. In addition, a low-noise charge sensing and sigma-delta modulator were designed for a high-precision digital output. The interfaced circuit with fully differential topology was fabricated in a$0.35 \mu \text{m}$standard complementary metal-oxide semiconductor (CMOS) process. The integrated accelerometers can achieve a power consumption of 7 mW from a 5 V supply at a sampling frequency of 256 kHz, a noise floor of −140 dBV below 400 Hz. The equivalent input noise voltage density is 250nV/$\surd $Hz, corresponding to a reference voltage of 2.5V. It can achieve an equivalent noise acceleration of$0.14 \mu \text{g}\surd $Hz and a bias instability of$9 \mu \text{g}$at a bandwidth of 400 Hz, a nonlinearity of 0.13% within ±1 g.

This paper presents a perception-aware decomposition and fusion framework for underwater image enhancement (UIE). Specifically, a general structural patch decomposition and fusion (SPDF) approach is introduced. SPDF is built upon the fusion of two complementary pre-processed inputs in a perception-aware and conceptually independent image space. First, a raw underwater image is pre-processed to produce two complementary versions including a contrast-corrected image and a detail-sharpened image. Then, each of them is decomposed into three conceptually independent components, i.e., mean intensity, contrast, and structure, via structural patch decomposition (SPD). Afterwards, the corresponding components are fused using tailored strategies. The three components after fusion are finally integrated via inverting the decomposition to reconstruct a final enhanced underwater image. The main advantage of SPDF is that two complementary pre-processed images are fused in a perception-aware and conceptually independent image space and the fusions of different components can be performed separately without any interactions and information loss. Comprehensive comparisons on two benchmark datasets demonstrate that SPDF outperforms several state-of-the-art UIE algorithms qualitatively and quantitatively. Moreover, the effectiveness of SPDF is also verified on another two relevant tasks, i.e., low-light image enhancement and single image dehazing. The code will be made available soon.

This study presents a technique for designing a multimode configurable weak physically unclonable function (PUF) for security-key generation. The PUF cell is based on the maximum gain point deviations of bias-voltage-controlled inverters. By implementing a preselection strategy, the proposed PUF can simultaneously expose all unstable cells under normal voltage and temperature. Owing to the configurable bias circuit, the PUF cell can be biased at three operating modes, namely, traditional inverter (INV), current-starved inverter (CSI), and power gating (PG). The measurement results from a 65-nm prototype show that the proposed PUF has the following outstanding features: 1) it has a compact cell layout with a minimum feature size of 966 F2; 2) an autocorrelation function of 0.0099 is achieved; and 3) all unstable cells can be eliminated using a preselection procedure, which can drastically reduce the energy and area costs for error correction. In addition, in the CSI mode, the proposed PUF (standard voltage) has maximum frequency and throughput of 714 MHz and 45.7 Gb/s, respectively. Meanwhile, under the INV mode, the worst native bit error rate (low voltage) for 5000 evaluations is only 0.33%, indicating a desirable instability against voltage and temperature variations with a sensitivity coefficient of 1.85%/V and 0.018%/°C, respectively. Moreover, the measured energy efficiency at 0.6 V is 6.83 fJ/bit. Finally, under the PG mode, the standby powers at 0.6 and 1.2 V are only 18 and 86 nW, respectively.

This article presents a novel class of bistable physically unclonable functions (PUFs) for security-oriented applications. The traditional cross-coupled bistable PUF cell is divided into P-net and N-net, wherein the P-net (N-net) multiplexing acts as the shared head (foot), and the N-net (P-net) duplicating multiple acts as the PUF cell. The proposed PUF was fabricated in a Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm process with full-custom design. It can parallelly generate 128-bit identifications (IDs) in one clock cycle owing to the random access word-level readout framework. The measurement results show that the randomness and uniqueness of the proposed PUF are consistent with those of the state-of-the-art works. In addition, the proposed PUF has the following features: 1) the PUF cell is composed only of four nMOS transistors with a minimum feature size of 215-F2; 2) the native bit instability at the golden condition (i.e., 1.2 V, 25 °C) with 500 evaluations is only 2.05%, showing a desirable native stability against supply noise; 3) the bit-error-rate dependences of the voltage and temperature are 3.35%/V and 0.011%/°C, respectively, with the voltage varying within the range 1.0-1.4 V and the temperature varying within the range -40 °C to 125 °C; 4) an autocorrelation function of 0.0049 at a 95% confidence level is achieved and is the lowest reported value to date; and 5) the energy efficiency and throughput at the maximum operating frequency (i.e., 433 MHz) are 99.48 fJ/b and 55.5 Gb/s, respectively.

Soft error protection is a paramount requirement for memories exposed to radiation environment. To satisfy the demand, a radiation-hardened new-quatro 10T memory cell is proposed in this brief, which is immune to single-node upset and also has high resilience to multinode upset while features read-disturbance-free benefiting from its internal quad-node interlocked feedback mechanism. Simulation results show that it provides ample radiation robustness to single event and gives 1.75× improvements in multinode upset tolerance when compared with the previous 12T dual-interlocked storage cell (DICE-12T) bitcell, signifying the higher fault tolerance capability. In addition, the proposed design also achieves 6.48× enhancement in read noise margin when compared with the DICE-12T bitcell while compromising only 2.1× larger area than a reference 6T cell based on a 65-nm logic design rule, exhibiting the superiority in read stability.

Emerging physical unclonable function (PUF) circuit designs in the IC supply chain pose not only a challenge to security threats but also a serious concern about hardware efficiency. The existing conventional PUF methods extract intrinsic random physical variation to generate two-valued secret key bits, which lack logical complexity and have poor efficiency in interconnect lines. This paper proposes a multiple-valued logic PUF circuit (MPUF), which focuses on adding logical complexity and minimizing hardware cost by processing on multilevel-cell and interconnect lines. The twins' cell is selected as the MPUF cell to source the multiple-valued physical variation, and the bit-line sharing strategy was integrated to implement the four-valued PUF data. After full-custom designing, the MPUF with 512 cells only needs 16 transmit bit lines. The proposed MPUF chip is fabricated under 65-nm CMOS technology and the core area occupies approximately 0.016 mm2with a 4.9-μm2bitcell size. The measured results show that the MPUF data passed National Institute of Standards and Technology randomness tests, and that it operates 0.1-pJ/b energy efficiency at 1.2 V, ensures randomness and uniqueness with 50.42% hamming distance, and less than 0.04 autocorrelation at 95% confidence level. Compared with other state of the arts, logical complexity improves 50% for resisting power attacks.

The Mote architecture is the most popular platform used in wireless sensor network applications. In this architecture, microcontroller is responsible for all jobs, such as scheduling, sampling, computing, and communication. In the past one year, two practical applications: bridge structural health monitoring system and rare animal monitoring system are developed and deployed in Wuxi and Beijing, China. It is found that Mote architecture faces many problems in these applications. First, sampling, computing, and communication conflicts with each other if they are not carefully scheduled; second, some jobs are very difficult even impossible to be implemented in the microcontroller; third, low power, one of the most fundamental design principles in wireless sensor networks, is sometimes violated with all jobs implemented in the microcontroller. Software optimization is attempted to solve these problems. However, the effect is very limited. Application specific sensor node architecture is necessary for implementing these applications efficiently. In this paper, we propose new application specific sensor node architecture and corresponding design principles and then applied them in the field deployments. Experimental and field tests show that these architectures are more efficient than Mote architecture in these applications.

In this study, the authors propose a new method for constructing irregular low-density parity-check codes (LDPC codes) with midterm or short block lengths. It is a Monte-Carlo simulation-based optimisation procedure called downhill simplex which uses progressive edge growth method for Tanner graph construction in cost function evaluations. It outperforms the density evolution (DE) method in both efficiency and performance. The efficiency of the authors' proposal mostly depends on the Monte-Carlo simulation time which owing to the midterm block lengths is relatively small compared to the time delay of the conventional DE method. Simulation results show that for block length of 3200 and a relatively low code rate 3/8, LDPC codes constructed using the authors' proposal noticeably outperform those constructed with DE method by more than 0.2 dB in the entire signal to noise ratio (SNR) range under AWGN channel.

Through the research on the decoding algorithm of low-density parity-check (LDPC) code, a low complexity decoding algorithm suitable for quasi-cyclic LDPC (QC-LDPC) code is proposed in this paper. The algorithm adopts layered decoding (LD), and the sub-minimum is replaced by the sum of an optimal correction factor and the minimum during the process of the check nodes update. Therefore, it is not required to find the sub-minimum and the computational complexity reduces significantly. Matlab simulation results show that the decoding performance of this algorithm is very near to min-sum (MS) algorithm, and more superior than single min-sum (SMS) algorithm.

Short-wave together with medium-and longwave broadcasting still has large listenership worldwide. With the newly developed digital system DRM will overcome these reception problems and bring high audio quality, which will change the whole broadcasting scenario. This paper will give an overview of DRM including its development history, the standardization, the receiving technology, the key features and state of the art. The emergence of DRM lights the way of digital radio ahead.