Fault diagnosis is critical for improving product yield and reducing manufacturing cost. However, it is very challenging to identify the root cause of failures on a complex circuit board. Ambiguous diagnosis results lead to long debug times and even wrong repair actions, which significantly increases the repair cost. We propose an automatic diagnostic system using support vector machines (SVMs). The proposed system acquires debug knowledge from empirical data; this strategy avoids the difficulties involved in knowledge acquisition in traditional fault diagnosis methods. SVMs provide an optimal separating hyperplane in classification. The optimal solution and generalization ability of SVMs lead to higher diagnostic accuracy, compared to the classical learning approaches such as artificial neural networks (ANNs). An industrial board is used to validate the effectiveness of the proposed system. Extensive simulation results demonstrate that the SVMs-based diagnostic system provides quantifiable improvement over current diagnostic software and an ANN-based diagnostic system.

Hardware fault insertion is a promising method for system reliability assessment and fault isolation. It provides feedback on the fault tolerance of a large system, creates artificial faulty scenarios that can be used as reference points for fault diagnosis, and leads to a quality diagnostic program. Optimization of fault insertion location is critical for accelerating the assessment of system reliability and constructing a complete knowledge base for fault diagnosis. In this work, we construct a pin-level fault model that is able to effectively mimic the errors (effects) caused by physical defects within the component. A simulation framework and optimization techniques are proposed to select a minimum subset of output pins that can represent as many physical defects as possible. The optimization results provide guidelines on the fault insertion locations and the appropriate fault types for insertion. In addition, three intrinsic characteristics of output pins, including testability number, fan-in size, and transition counts, are analyzed. The effectiveness of the proposed model is evaluated in terms of impact on system response and error-detection latency. Experimental results are presented for OpenCore benchmarks.

Diagnosis of functional failures at the board level is critical for improving product yield and reducing manufacturing cost. State-of-the-art board-level diagnostic software is unable to cope with high complexity and ever-increasing clock frequencies, and the identification of the root cause of failure on a board is a major problem today. Ambiguous or incorrect repair suggestions lead to long debug times and even wrong repair actions, which significantly increases the repair cost and adversely impacts yield. We propose a smart diagnosis method based on artificial neural networks that can learn from repair history and accurately localize the root cause of a failure. Fine-grained fault syndromes extracted from failure logs and the corresponding repair actions are used to train the neural network. The proposed network structure is simple, it can be rapidly trained, and it is scalable to large datasets. Moreover, the relationship between typical syndromes and the most appropriate repair actions can be easily inferred from the network structure. An industrial board, which is currently in production, is used to validate the diagnosis approach in terms of diagnostic accuracy, resolution, and quantifiable improvement over current diagnostic software.

Hardware fault-insertion test is a promising method to diagnose functional failures and target ''no trouble found (NTF)" problems in electronic systems. However, it is costly and impractical to equip all the potential fault sites with fault-insertion hardware. We present an optimization method to select the most effective outputs of a module where fault insertion logic must be placed to facilitate diagnosis. Faults inserted at the selected outputs are able to generate fault syndromes that are most similar to the errors produced by defects inside the module. This approach also ensures that the ambiguous fault candidates from other modules are maximally removed from the set of suspects. A fault syndrome is defined by the order of error occurrence at the observation points, and it is referred as an error flow. The similarity between two error flows is measured by the metric of edit distance. An integer linear programming model is used to maximize diagnostic effectiveness with a small number of fault-insertion points. Results on diagnostic accuracy for an open-source RISC highlight the effectiveness of the proposed method compared to a baseline random fault-insertion scheme.

Diagnosis of functional failures is critical for locating manufacturing defects, increasing yield, and reducing field returns. It is important to narrow down the defective module in a failed component during board-level diagnosis. In this paper, a generic fault-diagnosis method based on an error-flow dictionary is presented to identify the root cause of functional failures on a chip or board. Error propagation mimics actual dataflow in a circuit, thus it reflects the native (functional) mode of circuit operation. In contrast to conventional fault syndromes, error flow includes the failure information in terms of circuit functionality, which significantly facilitates the diagnosis of functional failures. In the proposed diagnosis procedure, error flow is first learned from a good circuit by intentionally inserting faults, and then the root cause of a failing circuit is determined by comparing the similarity between the pre-learned error flow and the error flow observed from the failing circuit. The similarity of two error flows is evaluated based on the length of the longest common subsequence in string matching. Results for an open-source RISC SoC and an industrial communication circuit highlight the effectiveness of the proposed method.

Increasing integration densities and high operating speeds are leading to subtle manifestations of defects at the board level. Board-level functional test is therefore necessary for product qualification. The diagnosis of functional failures is especially challenging, and the cost associated with board-level diagnosis is escalating rapidly. An effective and cost-efficient board-level diagnosis strategy is needed to reduce manufacturing cost and time-to-market, as well as to improve product quality. In this paper, we use Bayesian inference to develop a new board-level diagnosis framework that allows us to identify faulty devices or faulty modules within a device on a failing board with high confidence. Bayesian inference offers a powerful probabilistic method for pattern analysis, classification, and decision making under uncertainty. We apply this inference technique by first generating a database of fault syndromes obtained using fault-insertion test at the module pin level on a fault-free board, and then use this database along with the observed erroneous behavior of a failing board to infer the most likely faulty device. Results on a case study using an open-source RISC system-on-chip highlight the effectiveness of the proposed framework in terms of fault-localization accuracy and correctness of diagnosis.

This paper presents a test data compression scheme that can be used to further improve compressions achieved by linear-feedback shift register (LFSR) reseeding. The proposed compression technique can be implemented with very low hardware overhead. The test data to be stored in the automatic test equipment (ATE) memory are much smaller than that for previously published schemes, and the number of test patterns that need to be generated is smaller than other weighted random pattern testing schemes. The proposed technique can be extended to generate test patterns that achieve high n-detection fault coverage. This technique compresses a regular 1-detection test cube set instead of an n-detection test cube set, which is typically n times larger. Hence, the volume of compressed test data for n-detection test is comparable to that for 1-detection test. Experimental results on a large industry design show that over 1600X compression is achievable by the proposed scheme with the test sequence length, which is comparable to that of highly compacted deterministic patterns. Experimental results on n -detection test show that test patterns generated by the proposed decompressor can achieve very high 5-detection stuck-at fault coverage and high compression for large benchmark circuits.

Hardware fault-insertion test (FIT) is a promising method for system reliability test and diagnosis coverage measurement. It improves the speed of releasing a quality diagnostic program before manufacturing and provides feedbacks of fault tolerance of a very complicated large system. Certain level insufficient fault tolerance can be fixed in the current system but others may require ASIC or overall system architectural modifications. The FIT is achieved by introducing an artificial fault (defect modeling) at the pin level of a module to mimic any physical defect behavior within the module, such as SEU (single event upset) or escaped delay defect. We present a hardware architectural solution for pin fault insertion. We also present a simulation framework and optimization techniques for a subset of module pin selection for FIT, such that desired coverage are obtained under the constraints of limited FIT pins due to the costs of the associated implementation. Experimental results are presented for selected ISCAS and OpenCore benchmarks, as well as for an industrial circuit.

We present a system-on-chip (SOC) testing approach that integrates test data compression, test-access mechanism/test wrapper design, and test scheduling. An efficient linear feedback shift register (LFSR) reseeding technique is used as the compression engine. All cores on the SOC share a single on-chip LFSR. At any clock cycle, one or more cores can simultaneously receive data from the LFSR. Seeds for the LFSR are computed from the care bits for the test cubes for multiple cores. We also propose a scan-slice-based scheduling algorithm that attempts to maximize the number of care bits the LFSR can produce at each clock cycle, such that the overall test application time (TAT) is minimized. This scheduling method is static in nature because it requires predetermined test cubes. We also present a dynamic scheduling method that performs test compression during test generation. Experimental results for International Symposium on Circuits and Systems and International Workshop on Logic and Synthesis benchmark circuits, as well as industrial circuits, show that optimum TAT, which is determined by the largest core, can often be achieved by the static method. If structural information is available for the cores, the dynamic method is more flexible, particularly since the performance of the static compression method depends on the nature of the predetermined test cubes.

Linear feedback shift register (LFSR) reseeding forms the basis for many test-compression solutions. A seed can be computed for each test cube by solving a system of linear equations based on the feedback polynomial of the LFSR. Despite the availability of numerous LFSR-reseeding-based compression methods in the literature, relatively little is known about the effectiveness of these seeds for unmodeled defects, particularly since there are often several candidate seeds for a test cube. We use the recently proposed output deviation measure of the resulting patterns as a metric to select appropriate LFSR seeds. Experimental results are reported using test patterns for stuck-at and transition faults derived from selected seeds for the ISCAS-89 and the IWLS-05 benchmark circuits. These patterns achieve higher coverage for transition and stuck-open faults than patterns obtained using other seed-generation methods for LFSR reseeding. Given a pattern pair (p1,p2) for transition faults, we also examine the transition-fault coverage for launch on capture by usingp1andp2to separately compute output deviations. Results show thatp1tends to be better when there is a high proportion of do-not-care bits in the test cubes, whilep2is a more appropriate choice when the transition-fault coverage is high.

At-speed functional testing, delay testing, andn-detection test sets are being used today to detect deep submicrometer defects. However, the resulting test data volumes are too high; the 2005 International Roadmap for Semiconductors predicts that test-application times will be 30 times larger in 2010 than they are today. In addition, many new types of defects cannot be accurately modeled using existing fault models. Therefore, there is a need to model the quality of test patterns such that they can be quickly assessed for defect screening. Test selection is required to choose the most effective pattern sequences from large test sets. Current industry practice for test selection is based on fault grading, which is computationally expensive and must also be repeated for every fault model. Moreover, although efficient methods exist today, for fault-oriented test generation, there is a lack of understanding on how best to combine the test sets thus obtained, i.e., derive the most effective union of the individual test sets without simply taking all the patterns for each fault model. This paper presents the use of the output deviation as a surrogate coverage-metric for pattern modeling and test grading. A flexible, but general, probabilistic-fault model is used to generate a probability map for the circuit, which can subsequently be used for test-pattern reordering. The output deviations resulting from the probability map(s) are used as a coverage-metric to model test patterns; the higher the deviation, the better the quality of the test pattern. We show that, for the ISCAS benchmark circuits and as compared to other reordering methods, the proposed method provides ldquosteeperrdquo coverage curves for different fault models.

We present a selective encoding method that reduces test data volume and test application time for scan testing of intellectual property (IP) cores. This method encodes the slices of test data that are fed to the scan chains in every clock cycle. To driveNscan chains, we use onlyctester channels, wherec=lceillog2(N+1)rceil+2 . In the best case, we can achieve compression by a factor ofN/cusing only one tester clock cycle per slice. We derive a sufficient condition on the distribution of care bits that allows us to achieve the best-case compression. We also derive a probabilistic lower bound on the compression for a given care-bit density. Unlike popular compression methods such as embedded deterministic test (EDT), the proposed approach is suitable for IP cores because it does not require structural information for fault simulation, dynamic compaction, or interleaved test generation. The on-chip decoder is small, independent of the circuit under test and the test set, and it can be shared between different circuits. We present compression results for a number of industrial circuits and compare our results to other recent compression methods targeted at IP cores.

We present an SoC testing approach that integrates test data compression, TAM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as the compression engine. All cores on the SoC share a single on-chip LFSR. At any clock cycle, one or more cores can simultaneously receive data from the LFSR. Seeds for the LFSR are computed from the core bits from the test cubes for multiple cores. We also propose a scan-slice-based scheduling algorithm that tries to maximize the number of core bits the LFSR can produce at each clock cycle, such that the overall test application time is minimized. Experimental results for both ISCAS circuits and industrial circuits show that optimal test application time, which is determined by the largest core, can be achieved. The proposed approach has small hardware overhead and is easy to deploy. Only one LFSR, one phase shifter, and a few counters should be added to the SoC. The scheduling algorithm is also scalable for large industrial circuits. The CPU time for a large industrial design ranges from 1 to 30 minutes

LFSR reseeding forms the basis for many test compression solutions. A seed can be computed for each test cube by solving a system of linear equations based on the feedback polynomial of the LFSR. Despite the availability of numerous LFSR-reseeding-based compression methods in the literature, relatively little is known about the effectiveness of these seeds for unmodeled defects. We use the recently proposed output deviation measure of the resulting patterns as a metric to select appropriate LFSR seeds. Experimental results are reported using test patterns for stuck-at faults derived from selected seeds. These patterns achieve higher coverage for stuck-open and transition faults than patterns obtained using other methods.

This paper presents a test data compression scheme that combines weighted random pattern testing and LFSR reseeding. Test patterns generated by the proposed decompressor can achieve high n-detection fault coverage. The proposed technique computes weight sets from a set of test cubes that are generated by a traditional 1-detection ATPG tool. The computed weight sets are modified to achieve high ndetection fault coverage. The proposed decompressor can be implemented with low area overhead. Since the proposed technique requires no special ATPG that is customized for the proposed scheme, it can compress test patterns generated by any ATPG tool and generate test patterns from the compressed test data that achieve high n-detection fault coverage. Experimental results show that test patterns generated by the proposed decompressor can achieve very high 5- detection stuck-at fault coverage and high compression for large benchmark circuits

We present a built-in self-test (BIST) approach for full-scan designs that extracts the most frequently occurring sequences from deterministic test patterns. The extracted sequences are stored on-chip, and are used during test application. Three sets of test patterns are applied to the circuit under test during a BIST test session; these include pseudorandom patterns, semirandom patterns, and deterministic patterns. The semirandom patterns are generated based on the stored sequences and they are more likely to detect hard-to-detect faults than pseudorandom patterns. The deterministic patterns are encoded using either the stored sequences or the LFSR reseeding technique to reduce test data volume. We use the cluster analysis technique for sequence extraction to reduce the amount of data to be stored. Experimental results for the ISCAS-89 benchmark circuits show that the proposed approach often requires less on-chip storage and test data volume than other recent BIST methods.

Scan architectures, though widely used in modern designs for testing purpose, are expensive in test data volume and power consumption. To solve these problems, the authors propose in this paper to modify an existing test data compression technique so that it can simultaneously address test data volume and power consumption reduction for scan testing of embedded intellectual property (IP) cores. Compared to the initial solution that fill don't-care bits with the aim of reducing only test data volume, here the assignment is performed to minimize also the power consumption. The proposed power-aware test data compression technique is applied to the ISCAS'89 and ITC'99 benchmark circuits and on a number of industrial circuits. Results show that up to 20times reduction in test data volume and 95% test power reduction can be obtained simultaneously

Testing using n-detection test sets, in which a fault is detected by n (n > 1) input patterns, is being increasingly advocated to increase defect coverage. However, the data volume for an n-detection test set is often too large, resulting in high testing time and tester memory requirements. Test set selection is necessary to ensure that the most effective patterns are chosen from large test sets in a high-volume production testing environment. Test selection is also useful in a time-constrained wafer-sort environment. The authors use a probabilistic fault model and the theory of output deviations for test set selection - the metric of output deviation is used to rank candidate test patterns without resorting to fault grading. To demonstrate the quality of the selected patterns, experimental results were presented for resistive bridging faults and non-feedback zero-resistance bridging faults in the ISCAS benchmark circuits. Our results show that for the same test length, patterns selected on the basis of output deviations are more effective than patterns selected using several other methods

We present a probabilistic fault model that allows any number of gates in an integrated circuit to fail probabilistically. Tests for this fault model, determined using the theory of output deviations, can be used to supplement tests for classical fault models, thereby increasing test quality and reducing the probability of test escape. Output deviations can also be used for test selection, whereby the most effective test patterns can be selected from large test sets during time-constrained and high-volume production testing. Experimental results are presented to evaluate the effectiveness of patterns with high output deviations for the single stuck-at and bridging fault models

We propose a built-in self-test (BIST) procedure for nanofabrics based on chemically-assembled electronic nanotechnology. We also present a recovery procedure through which we can identify defect-free nanoblocks and switchblocks in the nanofabric under test. The proposed BIST and recovery procedures are based on the reconfiguration of the nanofabric to achieve complete fault coverage of different types of faults. We show that a large fraction of defect-free blocks can be recovered using a small number of BIST configurations. The proposed BIST procedure is well suited for regular and dense architectures that have high defect densities.

We propose a built-in self-test (BIST) procedure for nanofabrics implemented using chemically-assembled electronic nanotechnology. Several fault detection configurations are presented to target stuck-at faults, shorts, opens, and connection faults in nanoblocks and switchblocks. We also present an adaptive recovery procedure through which we can identify defect-free nanoblocks and switchblocks in the nanofabric-under-test. The proposed BIST, recovery, and defect tolerance procedures are based on the reconfiguration of the nanofabric to achieve complete fault coverage for different types of faults. We show that a large fraction of defect-free blocks can be recovered using a small number of BIST configurations. We also present simple bounds on the recovery that can be achieved for a given defect density. Simulation results are presented for various nanofabric sizes, different defect densities, and for random and clustered defects. The proposed BIST procedure is well suited for regular and dense architectures that have high defect densities

We present a selective encoding method that reduces test data volume and test application time for scan testing of intellectual property (IP) cores. This method encodes the slices of test data that are fed to the scan chains in every clock cycle. Unlike many prior methods, the proposed method does not encode all the specified (0s and 1s) and unspecified (don't-care) bits in a slice. For example, if a slice contains more 1s than 0s, only the 0s are encoded and all don't-cares are mapped to 1. We use only c tester channels, where c = [log2(N + 1)] + 2, to drive N scan chains. In the best case, we can achieve compression by a factor of N/c using only one tester clock cycle per slice. We derive an upper bound on the density of care bits (either 1s or 0s) that allows us to achieve the best-case compression. The pattern decompression is of the continuous-flow type because no complex handshakes are required between the tester and the chip. Unlike popular compression methods such as EDT and SmartBIST, the proposed approach is suitable for IP cores because it does not require structural information for fault simulation, dynamic compaction, or interleaved test generation. The on-chip decoder is small, independent of the circuit under test and the test set, and it can be shared between different circuits. We present compression results for a number of industrial circuits, and compare our results to other recent compression methods targeted at IP cores. We show that up to 28times reduction in test data volume and 20times reduction in testing time is obtained for these circuits